Patents by Inventor Hidehisa Tateoka

Hidehisa Tateoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5108783
    Abstract: A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: April 28, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Tanigawa, Hidehisa Tateoka, Keizo Sakiyama, Shigeo Ohnishi, Yoshimitsu Yamauchi, Kenichi Tanaka
  • Patent number: 5059550
    Abstract: A method for manufacturing a semiconductor device comprising:making a trench in a Si semiconductor substrate;forming on the surface of the substrate a thermal oxidation film a Si.sub.3 N.sub.4 film, and a SiO.sub.2 film by a chemical vapor deposition as a three-layered insulating film, in that order;forming a polysilicon layer to fill the trench;removing the polysilicon layer outside the trench; andperforming one of the following steps: (A) converting the exposed surface of the polysilicon layer in the trench to a SiO.sub.2 film, and removing the insulating film on the Si semiconductor substrate outside the trench; (B) removing the SiO.sub.2 layer of the insulating film, converting the exposed surface of the polysilicon layer in the trench to a SiO.sub.2 film, removing the Si.sub.3 N.sub.4 layer of the insulating film located above the opening of the trench, depositing a SiO.sub.2 film, and forming a side wall by leaving this SiO.sub.2 film only at the peripheral portion of the SiO.sub.
    Type: Grant
    Filed: October 24, 1989
    Date of Patent: October 22, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidehisa Tateoka, Shigeo Onishi, Kenichi Tanaka
  • Patent number: 4916087
    Abstract: A method of manufacturing a semiconductor device includes the steps of (a) depositing a first insulating film by an isotropic deposition method over the entire surface of a semiconductor substrate which is provided with a narrow trench having an opening width in submicrons and a broad trench having an opening width larger than 1 .mu.
    Type: Grant
    Filed: August 29, 1989
    Date of Patent: April 10, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidehisa Tateoka, Shigeo Onishi, Masato Kawai