Patents by Inventor Hidehito Kitakado

Hidehito Kitakado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230261578
    Abstract: Provided is a power conversion circuit and a control system in which radiated noise of the entire circuit is reduced. A power conversion circuit including at least: a switching element (e.g. a MOSFET, etc.) and a diode (e.g. a commutating diode, etc.): wherein the power conversion circuit is a single-switch power conversion; and the diode is a gallium oxide-based Schottky barrier diode.
    Type: Application
    Filed: March 30, 2023
    Publication date: August 17, 2023
    Inventors: Toshihiro IWAKI, Takuto IGAWA, Hidehito KITAKADO, Yusuke MATSUBARA
  • Publication number: 20230207431
    Abstract: Provided is a semiconductor device including, a plurality of PN junction diodes each having a negative temperature characteristic and connected to each other in series; a Schottky barrier diode having a positive temperature characteristic and connected to the PN junction diodes in parallel; and a die pad on which at least one of the PN junction diodes and the Schottky barrier diode are mounted commonly.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 29, 2023
    Inventors: Hideaki YANAGIDA, Takashi SHINOHE, Hiroyuki ANDO, Yusuke MATSUBARA, Hidehito KITAKADO
  • Publication number: 20230207541
    Abstract: Provided is a semiconductor device including, a plurality of PN junction diodes each having a negative temperature characteristic and connected to each other in series; a plurality of resistance elements connected respectively to the PN junction diodes in parallel and connected to each other in series; and a Schottky barrier diode having a positive temperature characteristic and connected to the PN junction diodes in parallel.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 29, 2023
    Inventors: Hideaki YANAGIDA, Takashi SHINOHE, Hiroyuki ANDO, Yusuke MATSUBARA, Hidehito KITAKADO
  • Publication number: 20230179095
    Abstract: Provided is a power conversion circuit including at least: a switching element that opens and closes an inputted voltage via a reactor; and a commutating diode that passes a current in a direction of an electromotive force by a voltage including at least the electromotive force generated from the reactor when the switching element is turned off, the commutating diode including a gallium oxide-based Schottky barrier diode.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 8, 2023
    Inventors: Hidehito KITAKADO, Yusuke MATSUBARA
  • Publication number: 20210020729
    Abstract: A display device has a plurality of pixels each including a drive transistor and an electro-optical element. A defective pixel repairing method of the display device includes electrically connecting an anode electrode of the electro-optical element in a defective pixel with the anode electrode of the electro-optical element in an adjacent normal pixel of same color, by irradiating a laser to an overlapping portion of two wirings formed in different wiring layers and having the overlapping portion via an insulating film in a plan view, to short-circuit the two wirings, and electrically disconnecting, in the defective pixel, the drive transistor from the electro-optical element. With this, the defective pixel can be repaired easily.
    Type: Application
    Filed: March 29, 2018
    Publication date: January 21, 2021
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: HIDEHITO KITAKADO
  • Patent number: 9910334
    Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Jun Koyama, Yukio Tanaka, Hidehito Kitakado, Hideto Ohnuma
  • Patent number: 9876033
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Patent number: 9812581
    Abstract: A semiconductor device (1001) includes an oxide semiconductor layer (7) and a conductor layer (13a, 13b, 13c, 13s) supported on a substrate (1). The oxide semiconductor layer (7) contains a first metallic element. The conductor layer (13a, 13b, 13c, 13s) has a multilayer structure including a first metal oxide layer (m1) containing the first metallic element, a second metal oxide layer (m2) on the first metal oxide layer, the second metal oxide layer (m2) containing an oxide of a second metallic element, and a metal layer (M) on the second metal oxide layer, the metal layer (M) containing the second metallic element. The first metal oxide layer (m1) and the oxide semiconductor layer (7) are made of the same oxide film. When viewed from the normal direction of the substrate 1, the first metal oxide layer (m1) and the oxide semiconductor layer (7) do not overlap.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 7, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hidehito Kitakado
  • Publication number: 20170213853
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei YAMAZAKI, Yukio YAMAUCHI, Hidehito KITAKADO
  • Patent number: 9620573
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Publication number: 20170052398
    Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.
    Type: Application
    Filed: August 26, 2016
    Publication date: February 23, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Jun KOYAMA, Yukio TANAKA, Hidehito KITAKADO, Hideto OHNUMA
  • Patent number: 9431431
    Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: August 30, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Jun Koyama, Yukio Tanaka, Hidehito Kitakado, Hideto Ohnuma
  • Patent number: 9240491
    Abstract: A semiconductor device (100A) has an oxide semiconductor layer (11). The oxide semiconductor layer (11) has a channel region (11c), and a source region (11s) and drain region (11d) positioned on respective sides of the channel region (11c). The source region (11s) has a low-resistance source region (11sx) that has a lower resistance than the channel region (11c), and the drain region (11d) has a low-resistance drain region (11dx) that has a lower resistance than the channel region (11c). The carrier concentrations of the low-resistance source region (11sx) and the low-resistance drain region (11dx) become progressively lower from a connecting portion between a source electrode (17) and the low-resistance source region (11sx) and a connecting portion between a drain electrode (18) and the low-resistance drain region (11dx) towards the channel region (11c).
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 19, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuatsu Ito, Hidehito Kitakado
  • Publication number: 20160013325
    Abstract: A semiconductor device (1001) includes an oxide semiconductor layer (7) and a conductor layer (13a, 13b, 13c, 13s) supported on a substrate (1). The oxide semiconductor layer (7) contains a first metallic element. The conductor layer (13a, 13b, 13c, 13s) has a multilayer structure including a first metal oxide layer (m1) containing the first metallic element, a second metal oxide layer (m2) on the first metal oxide layer, the second metal oxide layer (m2) containing an oxide of a second metallic element, and a metal layer (M) on the second metal oxide layer, the metal layer (M) containing the second metallic element. The first metal oxide layer (m1) and the oxide semiconductor layer (7) are made of the same oxide film. When viewed from the normal direction of the substrate 1, the first metal oxide layer (m1) and the oxide semiconductor layer (7) do not overlap.
    Type: Application
    Filed: February 25, 2014
    Publication date: January 14, 2016
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Hidehito KITAKADO
  • Patent number: 9235095
    Abstract: In an active matrix type liquid crystal display device, in which functional circuits such as a shift register circuit and a buffer circuit are incorporated on the same substrate, an optimal TFT structure is provided along with the aperture ratio of a pixel matrix circuit is increased. There is a structure in which an n-channel TFT, with a third impurity region which overlaps a gate electrode, is formed in a buffer circuit, etc., and an n-channel TFT, in which a fourth impurity region which does not overlap the gate electrode, is formed in a pixel matrix circuit. A storage capacitor formed in the pixel matrix circuit is formed by a light shielding film, a dielectric film formed on the light shielding film, and a pixel electrode. Al is especially used in the light shielding film, and the dielectric film is formed anodic oxidation process, using an Al oxide film.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: January 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Jun Koyama, Yukio Tanaka, Hidehito Kitakado
  • Patent number: 9236496
    Abstract: The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 12, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Sumio Katoh, Hidehito Kitakado
  • Patent number: 9209282
    Abstract: The present invention includes at least a step forming a source electrode (32) and a drain electrode (33), each of which is a multilayer film of a first conductive film (32a), (33a) made of titanium or molybdenum, a second conductive film (32b), (33b) made of copper, and a third conductive film (32c), (33c) made of titanium oxide, a step of forming passivation film (18), which is an inorganic insulating film, on an oxide semiconductor layer (13), the source electrode (32) and drain electrode (33), and an annealing step of annealing the oxide semiconductor layer (13).
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: December 8, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuatsu Ito, Hidehito Kitakado
  • Publication number: 20150255524
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Application
    Filed: May 12, 2015
    Publication date: September 10, 2015
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Patent number: 9105523
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Patent number: 9093541
    Abstract: The invention provides a thin film transistor having current driving force that can be substantially improved. By heat treatment, the IGZO layer (45) from which oxygen is taken away by the titanium electrodes (65) becomes the low resistance regions (40b), and the IGZO layer (45) from which oxygen is not taken away remains as the high resistance region (40a). In this state, when the gate voltage is applied to the gate electrode (20), electrons in the low resistance regions (40b) near the boundaries with the high resistance region (40a) move respectively to the titanium electrode (65) sides. As a result, the length of the low resistance regions (40b) becomes short, and oppositely, the length of the high resistance region (40a) becomes longer by the size of the shortened low resistance regions. However, the electrical channel length (Le) becomes shorter than the source/drain interval space (Lch) as the limit resolution of the exposure device, and the current driving force becomes large.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: July 28, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidehito Kitakado, Sumio Katoh