Patents by Inventor Hideho Inagawa

Hideho Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7929315
    Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: April 19, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hayashi, Hideho Inagawa
  • Patent number: 7902658
    Abstract: A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the first electrode pads. The second electrode pads include signal pads and power supply pads, and are arranged in rows along the semiconductor chip. All the power supply pads of the second electrode pads are for supplying power to the semiconductor chip and are disposed in a row positioned farther from the semiconductor chip than another row. Each power supply line that leads out from a second power supply pad has a width not less than a width of the second power supply pad.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Publication number: 20100128451
    Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.
    Type: Application
    Filed: January 27, 2010
    Publication date: May 27, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Seiji Hayashi, Hideho Inagawa
  • Patent number: 7679930
    Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: March 16, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hayashi, Hideho Inagawa
  • Publication number: 20090200666
    Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.
    Type: Application
    Filed: April 24, 2009
    Publication date: August 13, 2009
    Applicant: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Patent number: 7538441
    Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 26, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Publication number: 20090040741
    Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.
    Type: Application
    Filed: October 6, 2008
    Publication date: February 12, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Seiji Hayashi, Hideho Inagawa
  • Patent number: 7466560
    Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: December 16, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hayashi, Hideho Inagawa
  • Patent number: 7453699
    Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: November 18, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
  • Publication number: 20070235874
    Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.
    Type: Application
    Filed: June 19, 2007
    Publication date: October 11, 2007
    Inventor: Hideho Inagawa
  • Patent number: 7259467
    Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: August 21, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Publication number: 20070117427
    Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.
    Type: Application
    Filed: January 19, 2007
    Publication date: May 24, 2007
    Applicant: Canon Kabushiki Kaisha
    Inventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
  • Patent number: 7189923
    Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: March 13, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin′ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
  • Patent number: 7154050
    Abstract: A cable arranging structure for exchanging electric signals between a pair of printed circuit boards includes at least a pair of electrically conductive members adapted to arrange the cable between them over the entire length thereof. The electrically conductive members show an electric potential substantially equal to that of the ground. Such a structure requires only the two electrically conductive members to be rigidly secured so that radiant noises generated by the cable can be effectively suppressed by means of the structure without the need of deforming the cable.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 26, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Daishiro Sekijima, Hideho Inagawa, Satoshi Sugimoto, Seiji Hayashi, Shinichi Nishimura
  • Publication number: 20060050491
    Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.
    Type: Application
    Filed: September 2, 2005
    Publication date: March 9, 2006
    Applicant: Canon Kabushiki Kaisha
    Inventors: Seiji Hayashi, Hideho Inagawa
  • Publication number: 20050184403
    Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.
    Type: Application
    Filed: February 22, 2005
    Publication date: August 25, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hideho Inagawa
  • Publication number: 20050139369
    Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 30, 2005
    Applicant: CANON KABUSHIKI KAISHI
    Inventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
  • Publication number: 20040065472
    Abstract: A cable arranging structure for exchanging electric signals between a pair of printed circuit boards comprises at least a pair of electrically conductive members adapted to arrange the cable between them over the entire length thereof. The electrically conductive members show an electric potential substantially equal to that of the ground. Such a structure requires only the two electrically conductive members to be rigidly secured so that radiant noises generated by the cable can be effectively suppressed by means of the structure without the need of deforming the cable.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 8, 2004
    Inventors: Daishiro Sekijima, Hideho Inagawa, Satoshi Sugimoto, Seiji Hayashi, Shinichi Nishimura
  • Patent number: 6663432
    Abstract: This invention is directed to provide a shielded cable connector that can stabilize electrical connection between a cable-side shield member and a board-side ground pattern. In order to achieve this object, a shielded cable connector to be mounted on a shielded cable having a signal transmission line and a shield member around it includes a metal outer shell member to come into direct contact with the shield member. The outer shell member includes a contact portion extended to come into direct contact with a ground pattern of an electric board to which the shielded cable is to be connected.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: December 16, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Patent number: 6652320
    Abstract: A shielded cable with a connector, in which the connector is connected to an end portion of the shielded cable formed by covering a plurality of cores with a shielding member, comprises an electrode portion provided with a plurality of electrodes connected to the cores, a conductive inner housing having a fitting portion for fitting to a connector which is to be fitted to the connector, and having the electrode portion therein, and a conductive outer housing which is used in combination with the inner housing and contains cores exposed from the shielded cable, wherein the outer housing is electrically connected to the shielding member, and the outer housing is electrically connected to the inner housing through a conductive connecting portion electrically connected to the fitting portion of the inner housing.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideho Inagawa, Makoto Takayama, Toru Osaka, Tatsuo Nishino