Patents by Inventor Hideho Inagawa
Hideho Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7929315Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.Type: GrantFiled: January 27, 2010Date of Patent: April 19, 2011Assignee: Canon Kabushiki KaishaInventors: Seiji Hayashi, Hideho Inagawa
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Patent number: 7902658Abstract: A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the first electrode pads. The second electrode pads include signal pads and power supply pads, and are arranged in rows along the semiconductor chip. All the power supply pads of the second electrode pads are for supplying power to the semiconductor chip and are disposed in a row positioned farther from the semiconductor chip than another row. Each power supply line that leads out from a second power supply pad has a width not less than a width of the second power supply pad.Type: GrantFiled: April 24, 2009Date of Patent: March 8, 2011Assignee: Canon Kabushiki KaishaInventor: Hideho Inagawa
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Publication number: 20100128451Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.Type: ApplicationFiled: January 27, 2010Publication date: May 27, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Seiji Hayashi, Hideho Inagawa
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Patent number: 7679930Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.Type: GrantFiled: October 6, 2008Date of Patent: March 16, 2010Assignee: Canon Kabushiki KaishaInventors: Seiji Hayashi, Hideho Inagawa
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Publication number: 20090200666Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.Type: ApplicationFiled: April 24, 2009Publication date: August 13, 2009Applicant: Canon Kabushiki KaishaInventor: Hideho Inagawa
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Patent number: 7538441Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.Type: GrantFiled: June 19, 2007Date of Patent: May 26, 2009Assignee: Canon Kabushiki KaishaInventor: Hideho Inagawa
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Publication number: 20090040741Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.Type: ApplicationFiled: October 6, 2008Publication date: February 12, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Seiji Hayashi, Hideho Inagawa
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Patent number: 7466560Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.Type: GrantFiled: September 2, 2005Date of Patent: December 16, 2008Assignee: Canon Kabushiki KaishaInventors: Seiji Hayashi, Hideho Inagawa
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Patent number: 7453699Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.Type: GrantFiled: January 19, 2007Date of Patent: November 18, 2008Assignee: Canon Kabushiki KaishaInventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
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Publication number: 20070235874Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.Type: ApplicationFiled: June 19, 2007Publication date: October 11, 2007Inventor: Hideho Inagawa
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Patent number: 7259467Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.Type: GrantFiled: February 22, 2005Date of Patent: August 21, 2007Assignee: Canon Kabushiki KaishaInventor: Hideho Inagawa
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Publication number: 20070117427Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Applicant: Canon Kabushiki KaishaInventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
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Patent number: 7189923Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.Type: GrantFiled: December 23, 2004Date of Patent: March 13, 2007Assignee: Canon Kabushiki KaishaInventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin′ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
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Patent number: 7154050Abstract: A cable arranging structure for exchanging electric signals between a pair of printed circuit boards includes at least a pair of electrically conductive members adapted to arrange the cable between them over the entire length thereof. The electrically conductive members show an electric potential substantially equal to that of the ground. Such a structure requires only the two electrically conductive members to be rigidly secured so that radiant noises generated by the cable can be effectively suppressed by means of the structure without the need of deforming the cable.Type: GrantFiled: September 30, 2003Date of Patent: December 26, 2006Assignee: Canon Kabushiki KaishaInventors: Daishiro Sekijima, Hideho Inagawa, Satoshi Sugimoto, Seiji Hayashi, Shinichi Nishimura
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Publication number: 20060050491Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.Type: ApplicationFiled: September 2, 2005Publication date: March 9, 2006Applicant: Canon Kabushiki KaishaInventors: Seiji Hayashi, Hideho Inagawa
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Publication number: 20050184403Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.Type: ApplicationFiled: February 22, 2005Publication date: August 25, 2005Applicant: CANON KABUSHIKI KAISHAInventor: Hideho Inagawa
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Publication number: 20050139369Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.Type: ApplicationFiled: December 23, 2004Publication date: June 30, 2005Applicant: CANON KABUSHIKI KAISHIInventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
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Publication number: 20040065472Abstract: A cable arranging structure for exchanging electric signals between a pair of printed circuit boards comprises at least a pair of electrically conductive members adapted to arrange the cable between them over the entire length thereof. The electrically conductive members show an electric potential substantially equal to that of the ground. Such a structure requires only the two electrically conductive members to be rigidly secured so that radiant noises generated by the cable can be effectively suppressed by means of the structure without the need of deforming the cable.Type: ApplicationFiled: September 30, 2003Publication date: April 8, 2004Inventors: Daishiro Sekijima, Hideho Inagawa, Satoshi Sugimoto, Seiji Hayashi, Shinichi Nishimura
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Patent number: 6663432Abstract: This invention is directed to provide a shielded cable connector that can stabilize electrical connection between a cable-side shield member and a board-side ground pattern. In order to achieve this object, a shielded cable connector to be mounted on a shielded cable having a signal transmission line and a shield member around it includes a metal outer shell member to come into direct contact with the shield member. The outer shell member includes a contact portion extended to come into direct contact with a ground pattern of an electric board to which the shielded cable is to be connected.Type: GrantFiled: March 27, 2002Date of Patent: December 16, 2003Assignee: Canon Kabushiki KaishaInventor: Hideho Inagawa
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Patent number: 6652320Abstract: A shielded cable with a connector, in which the connector is connected to an end portion of the shielded cable formed by covering a plurality of cores with a shielding member, comprises an electrode portion provided with a plurality of electrodes connected to the cores, a conductive inner housing having a fitting portion for fitting to a connector which is to be fitted to the connector, and having the electrode portion therein, and a conductive outer housing which is used in combination with the inner housing and contains cores exposed from the shielded cable, wherein the outer housing is electrically connected to the shielding member, and the outer housing is electrically connected to the inner housing through a conductive connecting portion electrically connected to the fitting portion of the inner housing.Type: GrantFiled: December 13, 2002Date of Patent: November 25, 2003Assignee: Canon Kabushiki KaishaInventors: Hideho Inagawa, Makoto Takayama, Toru Osaka, Tatsuo Nishino