Abstract: A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the memory cell arrays than to the other of memory cell arrays, and the other of the main amplifiers is disposed closer to the other of the memory cell arrays than to the one of the memory cell arrays. Additional apparatus are disclosed.

Abstract: Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.

Abstract: Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.

Abstract: A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a reference potential. The second signal line is disposed in a first side of the first signal line. The second signal line is supplied with a second signal. The second signal is smaller in amplitude than the potential difference. The first shield line is disposed in a second side of the first signal line. The second side is opposite to the first side. The first shield line reduces a coupling noise that is applied to the first shield line from the second side.

Abstract: A method of manufacturing a semiconductor device includes: performing, in a case of manufacturing a first semiconductor device which operates by a first power supply voltage, at least one step from among channel ion implantation, gate oxide film formation, and gate electrode patterning according to a process of forming an element which operates with the first power supply voltage; performing, in a case of manufacturing a second semiconductor device which operates by a second power supply voltage, at least one step from among the channel ion implantation, the gate oxide film formation, and the gate electrode patterning according to a process of forming an element which operates with the second power supply voltage; and commonly performing at least diffusion region formation in the case of manufacturing the first semiconductor device and in the case of manufacturing the second semiconductor device.

Abstract: A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.

Abstract: A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a reference potential. The second signal line is disposed in a first side of the first signal line. The second signal line is supplied with a second signal. The second signal is smaller in amplitude than the potential difference. The first shield line is disposed in a second side of the first signal line. The second side is opposite to the first side. The first shield line reduces a coupling noise that is applied to the first shield line from the second side.

Abstract: A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are occupied by capacitors formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.