Patents by Inventor Hidekazu Kamioka

Hidekazu Kamioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7982266
    Abstract: A dielectrically isolated semiconductor device of high reliability is provided by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. The dielectrically isolated semiconductor device includes an SOI substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and an element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer, and which is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and a polycrystalline semiconductor layer formed between the second insulation films.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: July 19, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Mitsutoshi Honda, Norio Ishitsuka, Masahiro Ito, Toshihito Tabata, Shinichi Kurita, Hidekazu Kamioka
  • Publication number: 20070210408
    Abstract: It is an object of the present invention to provide an integrated circuit device structured to uniformly apply a voltage to side oxide films formed in a trench at both sides in an SOI substrate. The semiconductor integrated circuit device of the present invention comprises a substrate which supports a first insulation layer below an active device region, trench formed in the active device region to come into contact with the first insulation layer, second insulation film formed on the trench side wall, polycrystalline silicon with which the trench is filled, and third insulation film formed on the polycrystalline silicon, wherein the thickness ratio of the third insulation film to the first insulation film is 0.25 or more to uniformly apply a voltage to the oxide insulation films formed in the trench at both sides.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 13, 2007
    Inventors: Atsuo Watanabe, Mitsutoshi Honda, Norio Ishitsuka, Masahiro Ito, Toshihito Tabata, Shinichi Kurita, Hidekazu Kamioka