Patents by Inventor Hidekazu Nanzawa

Hidekazu Nanzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907579
    Abstract: A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell array having pages. The memory system is configured to execute a first operation method and a second operation method. The memory system includes a control information storage unit in which a first value is set for pages having a write operation speed that is slower than a first speed, and a second value is set for pages having a write operation speed that is equal to or higher than the first speed. The memory system is configured to, at the time of write operation, select the first operation method for a target page having the first value and perform the write operation using the first operation method, and select the second operation method for a target page having the second value and perform the write operation using the second operation method.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventor: Hidekazu Nanzawa
  • Patent number: 11847341
    Abstract: According to one embodiment, a memory card includes a nonvolatile memory including a data storage region and storing a table in which a logical address received from a host device is mapped to a physical address in the data storage region, and a controller configured to control the nonvolatile memory. The controller exchanges a first logical address with a second logical address based on a first command and data received from the host device.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Hidekazu Nanzawa, Tomoya Fukuzumi, Yuichi Emoto
  • Publication number: 20230088028
    Abstract: A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell array having pages. The memory system is configured to execute a first operation method and a second operation method. The memory system includes a control information storage unit in which a first value is set for pages having a write operation speed that is slower than a first speed, and a second value is set for pages having a write operation speed that is equal to or higher than the first speed. The memory system is configured to, at the time of write operation, select the first operation method for a target page having the first value and perform the write operation using the first operation method, and select the second operation method for a target page having the second value and perform the write operation using the second operation method.
    Type: Application
    Filed: February 1, 2022
    Publication date: March 23, 2023
    Inventor: Hidekazu NANZAWA
  • Publication number: 20220137862
    Abstract: According to one embodiment, a memory card includes a nonvolatile memory including a data storage region and storing a table in which a logical address received from a host device is mapped to a physical address in the data storage region, and a controller configured to control the nonvolatile memory. The controller exchanges a first logical address with a second logical address based on a first command and data received from the host device.
    Type: Application
    Filed: September 10, 2021
    Publication date: May 5, 2022
    Applicant: Kioxia Corporation
    Inventors: Hidekazu NANZAWA, Tomoya FUKUZUMI, Yuichi EMOTO
  • Publication number: 20210294899
    Abstract: According to one embodiment, a semiconductor device includes a memory controller and a memory device. The memory device stores firmware comprising a first portion and a second portion that is loaded after the first portion has been loaded at startup. The memory device also stores a stored authentication value that is based on the first portion of the firmware. The memory controller is configured to generate a authentication value from the first portion once the first portion has been loaded at startup.
    Type: Application
    Filed: September 1, 2020
    Publication date: September 23, 2021
    Inventors: Takeshi SAKAMOTO, Hidekazu Nanzawa, Seiji Matsumoto