Abstract: The present invention relates to a copper interconnection comprising a copper or copper alloy layer, wherein at least 50% of crystal grains of copper or a copper alloy form twins. A copper interconnection of the present invention is, therefore, highly reliable, and, a production cost thereof is low.

Abstract: A method for forming an interconnect comprises the steps of first covering an overall surface including a surface of a contact hole or a via-hole with a film of one of refractory metal and refractory metal compound and then depositing on the covered surface an aluminum film grown by a chemical vapor deposition (CVD) process using organic aluminum or trialkylamine-alane as a source material under a substrate temperature between 100.degree. C. and 180.degree. C. The organic aluminum is one of dimethylaluminum hydride, tri-isobutyl aluminum, trimethylamine-alane, and diethylaluminum hydride. The trialkylamine-alane is one of trimethylamine-alane and triethylamine-alane. Such aluminum film has good step-coverage so that, even when the diameter is small and the aspect ratio is high, the film can be deposited without an void being formed in the deposited film in the contact hole or the via-hole.

Abstract: A method for fabricating a semiconductor device comprises the steps of depositing a metal film for forming interconnections and/or electrodes on an insulating film formed on a substrate and then applying a hydrostatic pressure exceeding atmospheric pressure to the deposited metal film; or comprises the steps of forming a passivation film on a metal film for forming interconnections and/or electrodes, which is formed on a substrate with an insulating film, and then applying a hydrostatic pressure exceeding atmospheric pressure to the passivation film formed. The method makes it possible to substantially improve density and adhesion of the metal film and the insulating film and to produce semiconductor devices equipped with high-quality electrodes or interconnections at a relatively low cost.

Abstract: The present invention relates to a method of forming a diffused region with a shallow junction having a refractory metal silicide layer thereon. At first, the refractory metal silicide layer is selectively formed on a silicon substrate of one conductivity type. An insulating film is then formed at least on the refractory metal silicide layer, and a contact hole is opened on a part of the silicide layer. After necessary high temperature treatments have been conducted, a dopant impurity of the opposite conductivity type is introduced from the contact hole to the silicide layer. The impurity is laterally dispersed in the silicide layer and diffused into the whole portion of the silicon substrate in contact with the silicide layer, whereby the diffused region with a shallow junction can be formed.

Abstract: A process of forming electrodes and interconnections in a silicon semiconductor device comprises the steps of forming an insulating film on a silicon substrate, defining an opening in the insulating film, depositing a layer of metal having a high melting point on the insulating film, implanting ions to mix an interface between the metal layer and the silicon substrate, heating the construction in a temperature in the range of from 400 to 650 degrees Celsius to form a silicide of the metal layer in the opening, and selectively etching away an unreacted metal layer so as to self-align the silicide metal layer with the opening. The silicide metal layer is then annealed in a non-reducing gas atmosphere at a temperature ranging from 800 to 1,100 degrees Celsius.

Abstract: An integrated circuit device includes a first enhancement-type IGFET and a second depletion-type IGFET, each of which includes source and drain regions formed in the upper surface of a semiconductor substrate. Both IGFETs include a gate insulator film formed over their channel regions, the first IGFET having a high melting point metal gate electrode formed over its gate insulator without contacting the substrate surface and the second IGFET having a polycrystalline semiconductor gate electrode which directly contacts the substrate at a source/drain region common to the two IGFETs. Such a structure is used to form part of a semiconductor memory device having word lines of high melting point metal.