Patents by Inventor Hidekazu Satoh

Hidekazu Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6380014
    Abstract: A method of manufacturing a semiconductor device includes the step of forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode. The method further includes the step of depositing a silicon nitride film covering the insulated gate electrode over the semiconductor substrate by single wafer processing type thermal CVD at a substrate temperature of 500° to 800° C.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: April 30, 2002
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Ohta, Hidekazu Satoh
  • Patent number: 6268295
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film over a semicondutor substrate, introducing a reaction gas including a dilution gas into a reaction atmosphere and then growing a antireflection film made of silicon nitride or silicon nitride oxide on the first film by a plasma chemical vapor deposition method in the reaction atmosphere, coating resist on the antireflection film directly or via a second film and then patterning the resist via exposure and development, patterning the first film located in an area not covered with the resist by etching, and removing the antireflection film by use of hydrofluoric acid after patterning of the first film, whereby expansion of impurity diffusion can be prevented and also retreat of sidewalls can be suppressed.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: July 31, 2001
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Ohta, Hidekazu Satoh
  • Patent number: 6017784
    Abstract: A method of manufacturing a semiconductor device having fine MOS transistors includes a step of forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode, and a step of depositing an insulating film covering the insulated gate electrode over the semiconductor substrate, by parallel plate electrode plasma CVD using hydrogen-containing source gas under the conditions of a normalized RF power of 0.11 W/cm.sup.2 to 0.85 W/cm.sup.2 at the parallel plate electrode. A semiconductor device manufacture method is provided which can form fine MOS transistors of high reliability.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: January 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Ohta, Hidekazu Satoh