Patents by Inventor Hidekazu Takata
Hidekazu Takata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8704961Abstract: A display element and electronic element module according to the present invention is described, in which a lens is formed as part of a translucent support substrate having a display disposed thereon, the lens being formed on a part other than where the display is disposed, where an electronic element is disposed for the lens.Type: GrantFiled: August 5, 2009Date of Patent: April 22, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshitaka Okita, Hidekazu Takata, Masato Imanishi, Kazuya Fujita
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Publication number: 20100033647Abstract: A display element and electronic element module according to the present invention is described, in which a lens is formed as part of a translucent support substrate having a display disposed thereon, the lens being formed on a part other than where the display is disposed, where an electronic element is disposed for the lens.Type: ApplicationFiled: August 5, 2009Publication date: February 11, 2010Applicant: Sharp Kabushiki KaishaInventors: Yoshitaka Okita, Hidekazu Takata, Masato Imanishi, Kazuya Fujita
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Patent number: 7089427Abstract: A semiconductor storage device includes a program ROM and a flash memory, and the program ROM includes a program data storing area and a dummy data storing area, and the flash memory includes a program data storing area and a dummy address storing area. An address comparison circuit compares an input address and a dummy address being stored in the dummy address storing area with each other. An output inhibiting circuit allows to read program data from the program ROM when the both addresses are not coincident with each other, and inhibits the program data from being read at a time of incoincidence. In a case of the incoincidence, an address conversion circuit produces a read address of the flash memory, whereby the program data is read from the flash memory.Type: GrantFiled: November 28, 2000Date of Patent: August 8, 2006Assignees: Nintendo Co., Ltd., Sharp Kabushiki KaishaInventors: Hidekazu Takata, Yuji Tanaka
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Patent number: 6751716Abstract: A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a security circuit for controlling a security function which activates or deactivates at least a part of the memory space according to whether, in the case where an address input to the security-circuit matches at least one key-address included in the security circuit, data stored in the address in the memory space is manipulated under a condition equal to a predetermined condition or under a condition not equal to the predetermined condition.Type: GrantFiled: April 12, 2001Date of Patent: June 15, 2004Assignee: Sharp Kabushiki KaishaInventors: Ken Sumitani, Hidekazu Takata, Yuji Tanaka, Yasuyuki Aikawa
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Patent number: 6654303Abstract: A semiconductor memory device of the present invention includes: a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.Type: GrantFiled: June 11, 2002Date of Patent: November 25, 2003Assignee: Sharp Kabushiki KaishaInventors: Yasuo Miyamoto, Hidekazu Takata
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Patent number: 6594777Abstract: A semiconductor device includes: a read-only semiconductor memory device; and a nonvolatile semiconductor memory device for replacing defective data in at least one defective region which occurred in the read-only semiconductor memory device with modification data for modifying the defective data, the nonvolatile semiconductor memory device including: a memory section capable of electrically writing address data indicating an address of the defective region, and the modification data; and an address determination circuit for outputting a determination result signal which inactivates the read-only semiconductor memory device when the address data matches an address provided from outside the semiconductor memory device, wherein the nonvolatile semiconductor memory device reads and outputs the modification data from the memory section when the address data matches the address.Type: GrantFiled: February 17, 2000Date of Patent: July 15, 2003Assignee: Sharp Kabushiki KaishaInventor: Hidekazu Takata
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Patent number: 6573543Abstract: A reset device detects a rise of a supply voltage to start outputting a reset signal. The reset device includes a voltage detection circuit for detecting the supply voltage. The voltage detection circuit includes a ferroelectric capacitance element for detecting the supply voltage.Type: GrantFiled: September 28, 2001Date of Patent: June 3, 2003Assignee: Sharp Kabushika KaishaInventor: Hidekazu Takata
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Publication number: 20030062552Abstract: A reset device detects a rise of a supply voltage to start outputting a reset signal. The reset device includes a voltage detection circuit for detecting the supply voltage. The voltage detection circuit includes a ferroelectric capacitance element for detecting the supply voltage.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Hidekazu Takata
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Patent number: 6522581Abstract: A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.Type: GrantFiled: June 12, 2001Date of Patent: February 18, 2003Assignee: Sharp Kabushiki KaishaInventors: Hidekazu Takata, Haruyasu Fukui, Ken Sumitani
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Publication number: 20030007407Abstract: A semiconductor memory device of the present invention includes: a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.Type: ApplicationFiled: June 11, 2002Publication date: January 9, 2003Inventors: Yasuo Miyamoto, Hidekazu Takata
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Patent number: 6493278Abstract: A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.Type: GrantFiled: June 15, 2001Date of Patent: December 10, 2002Assignee: Sharp Kabushiki KaishaInventors: Hidekazu Takata, Ken Sumitani
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Patent number: 6469928Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cell array blocks including a first memory cell array block to which a data write operation is performed or from which a data erasure operation is performed, and a second memory cell array block from which a data read operation is performed concurrently with the data write operation or the data erasure operation to or from the first memory cell array block; and a plurality of block lock setting devices respectively provided in correspondence with the plurality of memory cell array blocks for placing the second memory cell array block into a locked state in which a data write operation to and a data erasure operation from the second memory cell array block is prohibited.Type: GrantFiled: March 28, 2001Date of Patent: October 22, 2002Assignee: Sharp Kabushiki KaishaInventor: Hidekazu Takata
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Patent number: 6400602Abstract: A semiconductor memory device includes: a plurality of memory cell regions, each comprising at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section. At least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.Type: GrantFiled: March 26, 2001Date of Patent: June 4, 2002Assignee: Sharp Kabushiki KaishaInventors: Hidekazu Takata, Kengo Maeda, Yasumichi Mori
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Patent number: 6370060Abstract: A semiconductor memory device includes a plurality of memory banks each including a plurality of memory cells, one of which is selectable in accordance with an address signal; a memory bit line for receiving a read voltage from the selected memory cell; a reference cell for outputting a reference voltage; a reference bit line for receiving the reference voltage; a comparison and amplification device for amplifying a difference between a voltage from the memory bit line and a voltage from the reference bit line; and a load capacitance adjusting device for providing a third load capacitance to the reference bit line so that a first load capacitance between the selected memory cell and the comparison and amplification device is substantially equal to a second load capacitance between the reference cell and the comparison and amplification device.Type: GrantFiled: April 17, 2001Date of Patent: April 9, 2002Assignee: Sharp Kabushiki KaishaInventors: Masahiro Takata, Hidekazu Takata
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Publication number: 20010055227Abstract: A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.Type: ApplicationFiled: June 15, 2001Publication date: December 27, 2001Inventors: Hidekazu Takata, Ken Sumitani
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Publication number: 20010053090Abstract: A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.Type: ApplicationFiled: June 12, 2001Publication date: December 20, 2001Inventors: Hidekazu Takata, Haruyasu Fukui, Ken Sumitani
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Publication number: 20010038554Abstract: A semiconductor memory device includes: a plurality of memory cell regions, each comprising at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section. At least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.Type: ApplicationFiled: March 26, 2001Publication date: November 8, 2001Inventors: Hidekazu Takata, Kengo Maeda, Yasumichi Mori
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Publication number: 20010036105Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cell array blocks including a first memory cell array block to which a data write operation is performed or from which a data erasure operation is performed, and a second memory cell array block from which a data read operation is performed concurrently with the data write operation or the data erasure operation to or from the first memory cell array block; and a plurality of block look setting devices respectively provided in correspondence with the plurality of memory cell array blocks for placing the second memory cell array block into a locked state in which a data write operation to and a data erasure operation from the second memory cell array block is prohibited.Type: ApplicationFiled: March 28, 2001Publication date: November 1, 2001Inventor: Hidekazu Takata
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Publication number: 20010033514Abstract: A semiconductor memory device includes a plurality of memory banks each including a plurality of memory cells, one of which is selectable in accordance with an address signal; a memory bit line for receiving a read voltage from the selected memory cell; a reference cell for outputting a reference voltage; a reference bit line for receiving the reference voltage; a comparison and amplification device for amplifying a difference between a voltage from the memory bit line and a voltage from the reference bit line; and a load capacitance adjusting device for providing a third load capacitance to the reference bit line so that a first load capacitance between the selected memory cell and the comparison and amplification device is substantially equal to a second load capacitance between the reference cell and the comparison and amplification device.Type: ApplicationFiled: April 17, 2001Publication date: October 25, 2001Inventors: Masahiro Takata, Hidekazu Takata
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Patent number: 6262910Abstract: A switching transistor is provided which applies predetermined voltage to a plurality of word lines based on a predetermined signal from a power on reset circuit, until predetermined potential becomes stable, when the predetermined potential is applied to the bit line or to the plate line, such as at the time of power on, to connect the bit line connected to each memory cell and the memory cell capacitor, as well as applies a control signal to the gate to thereby electrically connect the bit line and the plate line.Type: GrantFiled: October 13, 1999Date of Patent: July 17, 2001Assignee: Sharp Kabushiki KaishaInventors: Hidekazu Takata, Kengo Maeda