Patents by Inventor Hidekazu Tsuchida

Hidekazu Tsuchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220190114
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Application
    Filed: October 29, 2021
    Publication date: June 16, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Hidekazu TSUCHIDA, Koichi MURATA
  • Publication number: 20220173001
    Abstract: A SiC epitaxial wafer according to an embodiment includes: a SiC substrate; and a SiC epitaxial layer formed on a first surface of the SiC substrate. The in-plane uniformity of a density of Z1/2 centers of the SiC epitaxial layer is 5% or less.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: Showa Denko K.K.
    Inventors: Naoto ISHIBASHI, Koichi MURATA, Hidekazu TSUCHIDA
  • Publication number: 20220146564
    Abstract: A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 12, 2022
    Applicant: SHOWA DENKO K.K.
    Inventors: Koichi Murata, Isaho KAMATA, Hidekazu TSUCHIDA, Akira MIYASAKA
  • Publication number: 20220123112
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI
  • Publication number: 20220112623
    Abstract: A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 14, 2022
    Inventors: Norihiro HOSHINO, Isaho KAMATA, Hidekazu TSUCHIDA, Takahiro KANDA, Takeshi OKAMOTO
  • Patent number: 11183590
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tae Tawara, Shinji Fujikake, Aki Takigawa, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 11107892
    Abstract: A method for producing a SiC epitaxial wafer according to the present embodiment includes: an epitaxial growth step of growing the epitaxial layer on the SiC single crystal substrate by feeding an Si-based raw material gas, a C-based raw material gas, and a gas including a Cl element to a surface of a SiC single crystal substrate, in which the epitaxial growth step is performed under growth conditions that a film deposition pressure is 30 torr or less, a Cl/Si ratio is in a range of 8 to 12, a C/Si ratio is in a range of 0.8 to 1.2, and a growth rate is 50 ?m/h or more from an initial growth stage.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 31, 2021
    Assignees: SHOWA DENKO K.K., Central Research Institute Of Electric Power Industry, DENSO CORPORATION
    Inventors: Keisuke Fukada, Naoto Ishibashi, Akira Bando, Masahiko Ito, Isaho Kamata, Hidekazu Tsuchida, Kazukuni Hara, Masami Naito, Hideyuki Uehigashi, Hiroaki Fujibayashi, Hirofumi Aoki, Toshikazu Sugiura, Katsumi Suzuki
  • Publication number: 20210108334
    Abstract: In a silicon carbide single crystal wafer, a dislocation density contained therein is 3500 dislocations/cm2 or less, and a difference of the dislocation density among a wafer central part, a wafer peripheral part and a wafer intermediate part is less than 50% of an average value thereof.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 15, 2021
    Inventors: Isaho KAMATA, Hidekazu TSUCHIDA, Norihiro HOSHINO, Yuichiro TOKUDA, Takeshi OKAMOTO
  • Publication number: 20210102311
    Abstract: A silicon carbide single crystal contains a heavy metal element having a specific gravity higher than a specific gravity of iron. An addition density of the heavy metal element at least in an outer peripheral portion of the silicon carbide single crystal is set to 1×1015 cm?3 or more.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Yuichiro TOKUDA, Hideyuki UEHIGASHI, Norihiro HOSHINO, Hidekazu TSUCHIDA, Isaho KAMATA
  • Publication number: 20210074850
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.
    Type: Application
    Filed: August 3, 2020
    Publication date: March 11, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Tae TAWARA, Shinji FUJIKAKE, Aki TAKIGAWA, Hidekazu TSUCHIDA, Koichi MURATA
  • Patent number: 10896831
    Abstract: A supply part includes a first partition, a second partition under the first partition, a third partition under the second partition, a first flow path between the first partition and the second partition allowing a first gas to be introduced therein, a second flow path between the second partition and the third partition allowing a second gas to be introduced therein, a first piping extending from the second partition to reach below the third partition and being communicated with the first flow path, a second piping extending from the third partition to reach below the third partition and being communicated with the second flow path, and a convex portion provided on an outer circumferential surface of the first piping or an inner circumferential surface of the second piping protruding from one of the outer circumferential surface and the inner circumferential surface toward the other one.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 19, 2021
    Assignees: NuFlare Technology, Inc., Showa Denko K.K., Central Research Institute of Electric Power Industry
    Inventors: Kunihiko Suzuki, Naohisa Ikeya, Keisuke Fukada, Masahiko Ito, Isaho Kamata, Hidekazu Tsuchida, Hiroaki Fujibayashi, Hideyuki Uehigashi, Masami Naito, Kazukuni Hara, Hirofumi Aoki, Takahiro Kozawa
  • Patent number: 10868122
    Abstract: During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 ?m from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Koji Nakayama, Yoshiyuki Yonezawa, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 10748763
    Abstract: An n?-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n?-type epitaxial layer decreases and the n?-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa
  • Patent number: 10665681
    Abstract: On a front surface of an n+-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n+-type buffer layer, an n?-type drift layer, and a p+-type anode layer sequentially formed by epitaxial growth. The n+-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n+-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n+-type buffer layer.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20200083330
    Abstract: A method for producing a SiC epitaxial wafer according to the present embodiment includes: an epitaxial growth step of growing the epitaxial layer on the SiC single crystal substrate by feeding an Si-based raw material gas, a C-based raw material gas, and a gas including a Cl element to a surface of a SiC single crystal substrate, in which the epitaxial growth step is performed under growth conditions that a film deposition pressure is 30 torr or less, a Cl/Si ratio is in a range of 8 to 12, a C/Si ratio is in a range of 0.8 to 1.2, and a growth rate is 50 ?m/h or more from an initial growth stage.
    Type: Application
    Filed: April 19, 2018
    Publication date: March 12, 2020
    Applicants: SHOWA DENKO K.K., Central Research Institute of Electric Power Industry, DENSO CORPORATION
    Inventors: Keisuke FUKADA, Naoto ISHIBASHI, Akira BANDO, Masahiko ITO, Isaho KAMATA, Hidekazu TSUCHIDA, Kazukuni HARA, Masami NAITO, Hideyuki UEHIGASHI, Hiroaki FUJIBAYASHI, Hirofumi AOKI, Toshikazu SUGIURA, Katsumi SUZUKI
  • Patent number: 10584417
    Abstract: A film forming apparatus according to an embodiment of the invention includes: a film forming chamber configured to form a film on a substrate; a susceptor configured to place the substrate thereon; a rotating part configured to rotate the susceptor; a heater configured to heat the substrate; and a gas supplier configured to supply process gases into the film forming chamber, wherein the susceptor includes: a ring-shaped outer circumferential susceptor supported by the rotating part; a holder provided at an inner circumferential portion of the outer circumferential susceptor, the holder configured to hold the substrate; a ring-shaped plate provided over the outer circumferential susceptor; and a cover member configured to cover a top surface and an outer circumferential surface of the plate and an outer circumferential surface of the outer circumferential susceptor.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 10, 2020
    Assignee: NuFlare Technology, Inc.
    Inventors: Hideki Ito, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito, Masami Naito, Hiroaki Fujibayashi, Katsumi Suzuki, Koichi Nishikawa
  • Patent number: 10522667
    Abstract: The SiC-IGBT includes a p-type collector layer, an n?-type voltage-blocking-layer provided on the collector layer, p-type base regions provided on the n?-type voltage-blocking-layer, n+-type emitter regions provided in an upper portion of the p-type base region, a gate insulating film provided in an upper portion of the voltage-blocking-layer, and a gate electrode provided on the gate insulating film. The p-type buffer layer has thickness of five micrometers or more and 20 micrometers or less and is doped with Al at impurity concentration of 5×1017 cm?3 or more and 5×1018 cm?3 or less and doped with B at impurity concentration of 2×1016 cm?3 or more and less than 5×1017 cm?3.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20190393312
    Abstract: During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 ?m from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 26, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Koji Nakayama, Yoshiyuki Yonezawa, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20190376206
    Abstract: This SiC epitaxial wafer includes: a SiC single crystal substrate of which a main surface has an off-angle of 0.4° to 5° with respect to (0001) plane; and an epitaxial layer provided on the SiC single crystal substrate, wherein the epitaxial layer has a basal plane dislocation density of 0.1 pieces/cm2 or less that is a density of basal plane dislocations extending from the SiC single crystal substrate to an outer surface and an intrinsic 3C triangular defect density of 0.1 pieces/cm2 or less.
    Type: Application
    Filed: December 25, 2017
    Publication date: December 12, 2019
    Applicants: SHOWA DENKO K.K, Central Research Institute of Electric Power Industry, DENSO CORPORATION
    Inventors: Keisuke FUKADA, Naoto ISHIBASHI, Akira BANDO, Masahiko ITO, Isaho KAMATA, Hidekazu TSUCHIDA, Kazukuni HARA, Masami NAITO, Hideyuki UEHIGASHI, Hiroaki FUJIBAYASHI, Hirofumi AOKI, Toshikazu SUGIURA, Katsumi SUZUKI
  • Patent number: 10453924
    Abstract: A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa