Patents by Inventor Hidekazu Tsuchida

Hidekazu Tsuchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250215613
    Abstract: A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.
    Type: Application
    Filed: March 20, 2025
    Publication date: July 3, 2025
    Inventors: Norihiro HOSHINO, Isaho KAMATA, Hidekazu TSUCHIDA, Takahiro KANDA, Takeshi OKAMOTO
  • Patent number: 12297562
    Abstract: A silicon carbide ingot having micropipes in a seed crystal closed and being reduced in the gathering of screw dislocations, a method for manufacturing the silicon carbide ingot, and a method for manufacturing a silicon carbide wafer are provided. The silicon carbide ingot includes a seed crystal composed of a silicon carbide single crystal and having micropipes being hollow defects; a buffer layer provided on the seed crystal and composed of silicon carbide; and a bulk crystal growth layer provided on the buffer layer and composed of silicon carbide. The buffer layer and the bulk crystal growth layer have a plurality of screw dislocations continuous with the micropipes closed with the buffer layer, and the plurality of screw dislocations having the micropipe in common in the bulk crystal growth layer are 150 um or more apart from each other.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: May 13, 2025
    Assignees: 1)MIRISE Technologies Corporation, 2)DENSO CORPORATION, 3)TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Isaho Kamata, Norihiro Hoshino, Kiyoshi Betsuyaku, Hidekazu Tsuchida, Takeshi Okamoto, Akiyoshi Horiai
  • Patent number: 12281410
    Abstract: A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 22, 2025
    Assignees: CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY, DENSO CORPORATION
    Inventors: Norihiro Hoshino, Isaho Kamata, Hidekazu Tsuchida, Takahiro Kanda, Takeshi Okamoto
  • Patent number: 12252808
    Abstract: In a silicon carbide single crystal wafer, a dislocation density contained therein is 3500 dislocations/cm2 or less, and a difference of the dislocation density among a wafer central part, a wafer peripheral part and a wafer intermediate part is less than 50% of an average value thereof.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 18, 2025
    Assignee: DENSO CORPORATION
    Inventors: Isaho Kamata, Hidekazu Tsuchida, Norihiro Hoshino, Yuichiro Tokuda, Takeshi Okamoto
  • Patent number: 12249625
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 11, 2025
    Assignees: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Tawara, Tomonori Mizushima, Shinichiro Matsunaga, Kensuke Takenaka, Manabu Takei, Hidekazu Tsuchida, Kouichi Murata, Akihiro Koyama, Koji Nakayama, Mitsuru Sometani, Yoshiyuki Yonezawa, Yuji Kiuchi
  • Patent number: 12071709
    Abstract: A raw material gas is supplied to a space in which a silicon carbide seed crystal is placed. A silicon carbide single crystal is grown on the seed crystal by keeping a monosilane partial pressure at 4 kPa or more and heating the space to a temperature of 2400° C. to 2700° C. The temperature of the space and supply of the raw material gas are controlled such that a temperature gradient of a growth crystal surface of the silicon carbide single crystal in a radial direction is 0.1° C./mm or less, and a radius of curvature of the growth crystal surface is 4.5 m or more, thereby producing a silicon carbide single crystal ingot having a growth length of 3 mm or more and an internal stress of 10 MPa or less. The ingot is then cut into a silicon carbide single crystal wafer.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: August 27, 2024
    Assignee: DENSO CORPORATION
    Inventors: Isaho Kamata, Hidekazu Tsuchida, Norihiro Hoshino, Yuichiro Tokuda, Takeshi Okamoto
  • Publication number: 20240191392
    Abstract: A manufacturing method of a silicon carbide single crystal includes growing the silicon carbide single crystal on a surface of a seed crystal by supplying a supply gas including a raw material gas of silicon carbide to the surface of the seed crystal and controlling an environment so that at least a part inside the heating vessel is 2500° C. or higher. The growing the silicon carbide single crystal includes controlling a temperature distribution ?T in a radial direction centering on central axis of the seed crystal and the silicon carbide single crystal satisfies a radial direction temperature condition of ?T?10° ° C. on the surface of the seed crystal before the growing of the silicon carbide single crystal and on a growth surface of the silicon carbide single crystal during the growing of the silicon carbide single crystal.
    Type: Application
    Filed: February 27, 2024
    Publication date: June 13, 2024
    Inventors: Akiyoshi HORIAI, Takeshi OKAMOTO, Takahiro KANDA, Norihiro HOSHINO, Kiyoshi BETSUYAKU, Isaho KAMATA, Hidekazu TSUCHIDA, Takashi KANEMURA
  • Publication number: 20240110309
    Abstract: Provided are a method for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot which ensure a high crystal growth rate and increase the ratio of conversion from basal plane dislocations to threading edge dislocations. The method prepares a seed substrate composed of silicon carbide having an off-angle in a [1-100] direction with respect to a {0001} plane; and grows a silicon carbide single crystal layer on the seed substrate by an HTCVD method, thereby converting basal plane dislocations contained in the seed substrate to threading edge dislocations during crystal growth.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 4, 2024
    Inventors: Kiyoshi BETSUYAKU, Norihiro HOSHINO, Isaho KAMATA, Hidekazu TSUCHIDA, Akiyoshi HORIAI, Takeshi OKAMOTO
  • Publication number: 20240110308
    Abstract: Provided are a method for manufacturing a silicon carbide single crystal, which can suppress conversion of threading edge dislocations into prismatic plane dislocations and conversion of the prismatic plane dislocations into basal plane dislocations; and a silicon carbide single crystal ingot and a silicon carbide wafer, in which conversion from threading edge dislocations into prismatic plane dislocations and conversion from the prismatic plane dislocations into basal plane dislocations have been suppressed. A silicon carbide single crystal is grown on the surface of a seed substrate by a gas method so that a temperature gradient in the radial direction of the seed substrate takes a predetermined value or lower during the growth.
    Type: Application
    Filed: September 15, 2023
    Publication date: April 4, 2024
    Inventors: Kiyoshi BETSUYAKU, Norihiro HOSHINO, Isaho KAMATA, Hidekazu TSUCHIDA, Takeshi OKAMOTO, Takahiro KANDA
  • Patent number: 11948976
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 11906569
    Abstract: A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 20, 2024
    Assignee: SHOWA DENKO K.K.
    Inventors: Koichi Murata, Isaho Kamata, Hidekazu Tsuchida, Akira Miyasaka
  • Patent number: 11846040
    Abstract: A silicon carbide single crystal contains a heavy metal element having a specific gravity higher than a specific gravity of iron. An addition density of the heavy metal element at least in an outer peripheral portion of the silicon carbide single crystal is set to 1×1015 cm?3 or more.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: December 19, 2023
    Assignees: DENSO CORPORATION, CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY
    Inventors: Yuichiro Tokuda, Hideyuki Uehigashi, Norihiro Hoshino, Hidekazu Tsuchida, Isaho Kamata
  • Publication number: 20230374699
    Abstract: A raw material gas is supplied to a space in which a silicon carbide seed crystal is placed. A silicon carbide single crystal is grown on the seed crystal by keeping a monosilane partial pressure at 4 kPa or more and heating the space to a temperature of 2400° C. to 2700° C. The temperature of the space and supply of the raw material gas are controlled such that a temperature gradient of a growth crystal surface of the silicon carbide single crystal in a radial direction is 0.1° C./mm or less, and a radius of curvature of the growth crystal surface is 4.5 m or more, thereby producing a silicon carbide single crystal ingot having a growth length of 3 mm or more and an internal stress of 10 MPa or less. The ingot is then cut into a silicon carbide single crystal wafer.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Isaho KAMATA, Hidekazu TSUCHIDA, Norihiro HOSHINO, Yuichiro TOKUDA, Takeshi OKAMOTO
  • Publication number: 20230279580
    Abstract: A manufacturing method of a silicon carbide single crystal includes growing the silicon carbide single crystal on a surface of a seed crystal by supplying a supply gas including a raw material gas of silicon carbide to the surface of the seed crystal and controlling an environment so that at least a part inside the heating vessel is 2500° C. or higher. The growing the silicon carbide single crystal includes controlling a temperature distribution ?T in a radial direction centering on central axis of the seed crystal and the silicon carbide single crystal satisfies a radial direction temperature condition of ?T?10° C. on the surface of the seed crystal before the growing of the silicon carbide single crystal and on a growth surface of the silicon carbide single crystal during the growing of the silicon carbide single crystal.
    Type: Application
    Filed: January 30, 2023
    Publication date: September 7, 2023
    Inventors: Akiyoshi HORIAI, Takeshi OKAMOTO, Takahiro KANDA, Norihiro HOSHINO, Kiyoshi BETSUYAKU, Isaho KAMATA, Hidekazu TSUCHIDA, Takashi KANEMURA
  • Publication number: 20230193510
    Abstract: A silicon carbide ingot having micropipes in a seed crystal closed and being reduced in the gathering of screw dislocations, a method for manufacturing the silicon carbide ingot, and a method for manufacturing a silicon carbide wafer are provided. The silicon carbide ingot comprises: a seed crystal composed of a silicon carbide single crystal and having micropipes being hollow defects; a buffer layer provided on the seed crystal and composed of silicon carbide; and a bulk crystal growth layer provided on the buffer layer and composed of silicon carbide. The buffer layer and the bulk crystal growth layer have a plurality of screw dislocations continuous with the micropipes closed with the buffer layer, and the plurality of screw dislocations having the micropipe in common in the bulk crystal growth layer are 150 ?m or more apart from each other.
    Type: Application
    Filed: November 30, 2022
    Publication date: June 22, 2023
    Inventors: Isaho KAMATA, Norihiro HOSHINO, Kiyoshi BETSUYAKU, Hidekazu TSUCHIDA, Takeshi OKAMOTO, Akiyoshi HORIAI
  • Patent number: 11600538
    Abstract: A SiC epitaxial wafer according to an embodiment includes: a SiC substrate; and a SiC epitaxial layer formed on a first surface of the SiC substrate. The in-plane uniformity of a density of Z1/2 centers of the SiC epitaxial layer is 5% or less.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 7, 2023
    Assignee: SHOWA DENKO K.K.
    Inventors: Naoto Ishibashi, Koichi Murata, Hidekazu Tsuchida
  • Publication number: 20220190114
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Application
    Filed: October 29, 2021
    Publication date: June 16, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Hidekazu TSUCHIDA, Koichi MURATA
  • Publication number: 20220173001
    Abstract: A SiC epitaxial wafer according to an embodiment includes: a SiC substrate; and a SiC epitaxial layer formed on a first surface of the SiC substrate. The in-plane uniformity of a density of Z1/2 centers of the SiC epitaxial layer is 5% or less.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: Showa Denko K.K.
    Inventors: Naoto ISHIBASHI, Koichi MURATA, Hidekazu TSUCHIDA
  • Publication number: 20220146564
    Abstract: A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 12, 2022
    Applicant: SHOWA DENKO K.K.
    Inventors: Koichi Murata, Isaho KAMATA, Hidekazu TSUCHIDA, Akira MIYASAKA
  • Publication number: 20220123112
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI