Abstract: Provided are ophthalmologic image processing method, including an acquisition step of acquiring OCT data of an eye to be examined based on a spectral interference signal output from an OCT optical system, a setting step of setting a depth region including an image position of a tissue as an extraction region for data on one-direction side from a zero delay position in the OCT data, and a display control step of extracting extracted OCT data corresponding to the extraction region from the OCT data and displaying the extracted OCT data in a display region set in advance on a monitor, and an OCT apparatus that executes the method.

Abstract: An ophthalmologic imaging method is implemented by an control unit of an ophthalmologic imaging device for acquiring entire image data of the tissue by repeatedly performing the steps of: setting a scanning position; acquiring the partial image data by applying, to an optical scanning unit, a driving signal that causes the optical scanning unit to scan light on a tissue of a subject eye at the scanning position that was set this time; and continuously operating the optical scanning unit after capturing the partial image data based on the scanning position that was set this time was completed by applying, to the optical scanning unit, a continuous driving signal.

Abstract: Provided are ophthalmologic image processing method, including an acquisition step of acquiring OCT data of an eye to be examined based on a spectral interference signal output from an OCT optical system, a setting step of setting a depth region including an image position of a tissue as an extraction region for data on one-direction side from a zero delay position in the OCT data, and a display control step of extracting extracted OCT data corresponding to the extraction region from the OCT data and displaying the extracted OCT data in a display region set in advance on a monitor, and an OCT apparatus that executes the method.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: An optical coherence tomography device includes an OCT optical system that irradiates a tissue of the subject's eye with measurement light from a light source, and detects interference between reference light and the measurement light reflected from the tissue by using a detector, and a processor, in which the processor performs a generation process of acquiring A-scan data based on a signal output from the detector in a cycle of 300 kilohertz or more and generating three-dimensional OCT data at any time based on the acquired A-scan data, and performs an analysis process on each piece of the three-dimensional OCT data generated at any time through the generation process, so as to output a real-time analysis result of the three-dimensional OCT data which is generated at any time.

Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

Abstract: In a process of implanting ions of an n-type impurity for threshold control into a semiconductor substrate surrounded by an element isolation portion, a resist pattern is formed such that the resist pattern covers a divot formed at a boundary portion of the element isolation portion with an SOI layer. Thus, since ions of the n-type impurity are not implanted into the divot, an etching rate of the divot in a cleaning process or the like is not accelerated, and etching can be suppressed. As a result, a BOX layer is prevented from becoming thin, so that degradation of a TDDB characteristic of the BOX layer can be prevented.

Abstract: An optical coherence tomography device includes an OCT optical system that irradiates a tissue of the subject's eye with measurement light from a light source, and detects interference between reference light and the measurement light reflected from the tissue by using a detector, and a processor, in which the processor performs a generation process of acquiring A-scan data based on a signal output from the detector in a cycle of 300 kilohertz or more and generating three-dimensional OCT data at any time based on the acquired A-scan data, and performs an analysis process on each piece of the three-dimensional OCT data generated at any time through the generation process, so as to output a real-time analysis result of the three-dimensional OCT data which is generated at any time.

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract: An ophthalmic photographing apparatus including an OCT optical system for acquiring an OCT signal of a subject eye; an optical scanner for scanning the subject eye by the measurement light applied to the subject eye; a scan controller for controlling driving of the optical scanner and operate first scan control of respectively performing one scan by measurement light with respect to each of plural scan lines and second scan control of performing plural scans by measurement light with respect to each of the plural scan lines; and an image processor for acquiring the OCT signal in each scan line based on an output signal from the OCT optical system and perform composite processing on a plurality of the OCT signals of each scan line acquired by the second scan control using the OCT signal of each scan line acquired by the first scan control as a template.

Abstract: Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits of the next stage of an I/O buffer circuit.

Abstract: Oxynitridation processing for heat treating a substrate in an atmosphere containing NO (nitrogen monoxide) and ion implantation of nitrogen are used in combination to control the concentration of nitrogen introduced near the boundary between a gate oxide film and a substrate (well), in the order of higher concentration given as: n-channel MISFET having a thick gate oxide film>n-channel MISFET having a thin gate oxide film>p-channel MISFET having the thick gate oxide film, p-channel MISFET having the thin gate oxide film, with no additional use of photomasks, whereby reliability to hot carriers and reliability to NBT can be compatibilized by optimizing the concentration of nitrogen introduced to the boundary between the gate oxide films of four types of MISFET of different conduction type and different gate oxide film thickness and the substrate (well).

Abstract: Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits subsequent to the next stage of an I/O buffer circuit.