Patents by Inventor Hideki Awata

Hideki Awata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11681051
    Abstract: The presence or absence of a preamble is detected with accuracy in a reception apparatus that receives a signal including a preamble. A reception section receives a subframe including a subframe preamble and a message and a frame including a frame preamble. A processing section performs a process of detecting the presence or absence of the subframe preamble according to whether or not a given relation holds between a reception timing of the subframe preamble and a reception timing of the frame preamble. A message decoding section extracts the message from the subframe and decodes the message in a case where the presence of the subframe preamble is detected.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 20, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kazukuni Takanohashi, Tetsuhiro Futami, Katsuyuki Tanaka, Hideki Awata, Shinji Inoue, Tsunetomo Nakazato
  • Publication number: 20220035046
    Abstract: The presence or absence of a preamble is detected with accuracy in a reception. apparatus that receives a signal including a preamble. A reception section receives a subframe including a subframe preamble and a message and a frame including a frame preamble. A processing section performs a process of detecting the presence or absence of the subframe preamble according to whether or not a given relation holds between a reception timing of the subframe preamble and a reception timing of the frame preamble. A message decoding section extracts the message from the subframe and decodes the message in a case where the presence of the subframe preamble is detected.
    Type: Application
    Filed: June 5, 2019
    Publication date: February 3, 2022
    Inventors: Kazukuni Takanohashi, Tetsuhiro Futami, Katsuyuki Tanaka, Hideki Awata, Shinji Inoue, Tsunetomo Nakazato
  • Patent number: 10591953
    Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 17, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Sotaro Ohara, Katsuyuki Tanaka, Katsumi Takaoka, Keita Izumi, Suguru Houchi, Gaku Hidai, Yutaka Takagi, Hideki Takahashi, Hideki Awata, Yasushi Katayama, Naoki Yoshimochi, Toshimasa Shimizu
  • Publication number: 20180210487
    Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Inventors: SOTARO OHARA, KATSUYUKI TANAKA, KATSUMI TAKAOKA, KEITA IZUMI, SUGURU HOUCHI, GAKU HIDAI, YUTAKA TAKAGI, HIDEKI TAKAHASHI, HIDEKI AWATA, YASUSHI KATAYAMA, NAOKI YOSHIMOCHI, TOSHIMASA SHIMIZU
  • Patent number: 8692713
    Abstract: To provide a receiving device which is capable of reducing average power and peak power by holding pseudo synchronization of a satellite signal during a sleep period. Provided is a receiving device including a receiving unit for receiving a signal from a satellite, a frequency conversion unit for converting a frequency of the received signal into a predetermined intermediate frequency, a synchronization acquisition unit for carrying out synchronization acquisition and for detecting a carrier frequency, and a synchronization holding unit for assigning and setting, per satellite, a phase of the spread code and the carrier frequency to each of a plurality of channels independently provided in a corresponding manner to a plurality of the satellites to synchronously hold the spread code and a carrier and also for demodulating a message included in the intermediate frequency.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventors: Katsuyuki Tanaka, Hideki Takahashi, Hideki Awata
  • Publication number: 20130093621
    Abstract: Provided is a receiving device, including a receiving unit that receives a signal from a satellite in a GPS, a frequency converting unit that converts a frequency of a reception signal received by the receiving unit into a predetermined IF, a synchronization acquiring unit that performs synchronization acquisition for detecting a phase of a spread code in the IF signal and detects a carrier frequency in the IF signal, a synchronization holding unit that assigns and sets the phase of the spread code and the carrier frequency detected by the synchronization acquiring unit to a plurality of channels, holds synchronization of the spread code and a carrier using the set phase of the spread code and the carrier frequency, and demodulates a message included in the IF signal, and a control unit that executes operation control including a positioning calculation using the message demodulated by the synchronization holding unit.
    Type: Application
    Filed: July 28, 2011
    Publication date: April 18, 2013
    Applicant: SONY CORPORATION
    Inventors: Katsuyuki Tanaka, Hideki Awata, Hideki Takahashi
  • Publication number: 20130094541
    Abstract: To provide a receiving device which is capable of reducing average power and peak power by holding pseudo synchronization of a satellite signal during a sleep period. Provided is a receiving device including a receiving unit for receiving a signal from a satellite, a frequency conversion unit for converting a frequency of the received signal into a predetermined intermediate frequency, a synchronization acquisition unit for carrying out synchronization acquisition and for detecting a carrier frequency, and a synchronization holding unit for assigning and setting, per satellite, a phase of the spread code and the carrier frequency to each of a plurality of channels independently provided in a corresponding manner to a plurality of the satellites to synchronously hold the spread code and a carrier and also for demodulating a message included in the intermediate frequency.
    Type: Application
    Filed: July 6, 2011
    Publication date: April 18, 2013
    Applicant: SONY CORPORATION
    Inventors: Katsuyuki Tanaka, Hideki Takahashi, Hideki Awata
  • Patent number: 8351470
    Abstract: A signal receiver including an input that receives a plurality of signals from a respective plurality of channels; a multiplexer unit that receives the plurality of signals from the input and that selects, in a time-division manner, one of the plurality of signals; and at least one phase difference detector that receives the selected signal from the multiplexer unit, a number of the at least one phase difference detectors being less than a number of the plurality of channels.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: January 8, 2013
    Assignee: Sony Corporation
    Inventors: Hideki Awata, Hideki Takahashi
  • Patent number: 8222935
    Abstract: A communication system includes a phase-locked loop that maintains synchronization of a reception signal. The phase-locked loop includes a loop filter that has a circuit configuration m for an m-th order phase-locked loop including a circuit configuration n for an n-th order phase-locked loop (m>n), and a switching section that switches circuit configurations, which are activated in the loop filter, between the circuit configuration n and the circuit configuration m.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: July 17, 2012
    Assignee: Sony Corporation
    Inventor: Hideki Awata
  • Patent number: 8144751
    Abstract: A satellite signal receiver apparatus by which the hardware scale can be suppressed while high speed synchronization is assured. A carrier frequency component is removed from a satellite signal. Then, adding those of signals obtained after every period interval of spread spectrum codes and signals stored in a memory which have a same phase at the period intervals and writing an addition result back into the memory are repeated by a number of times corresponding to plural periods thereby to accumulate signals corresponding to sums of the signals added over the plural periods at the period intervals into the memory. Then, correlation calculation is performed between the signals for the one period of the spread spectrum codes corresponding to the plural periods and a spread spectrum code of the receiver side to detect a correlation point between the satellite signal and the receiver side spread spectrum code.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: March 27, 2012
    Assignee: Sony Corporation
    Inventors: Manabu Nitta, Hideki Awata, Hideki Takahashi
  • Publication number: 20100329237
    Abstract: A signal receiver including an input that receives a plurality of signals from a respective plurality of channels; a multiplexer unit that receives the plurality of signals from the input and that selects, in a time-division manner, one of the plurality of signals; and at least one phase difference detector that receives the selected signal from the multiplexer unit, a number of the at least one phase difference detectors being less than a number of the plurality of channels.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 30, 2010
    Applicant: Sony Corporation
    Inventors: Hideki Awata, Hideki Takahashi
  • Publication number: 20100253402
    Abstract: A communication system includes a phase-locked loop that maintains synchronization of a reception signal. The phase-locked loop includes a loop filter that has a circuit configuration m for an m-th order phase-locked loop including a circuit configuration n for an n-th order phase-locked loop (m>n), and a switching section that switches circuit configurations, which are activated in the loop filter, between the circuit configuration n and the circuit configuration m.
    Type: Application
    Filed: February 26, 2010
    Publication date: October 7, 2010
    Applicant: SONY CORPORATION
    Inventor: Hideki AWATA
  • Publication number: 20090243928
    Abstract: There is provided an information processing apparatus arranged with a satellite position estimating section for estimating a position of an artificial satellite at an arbitrary time by substituting the arbitrary time to an estimate equation of the position of the artificial satellite represented by a sum of one, or two or more periodic functional arguments.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventors: Shizuhiro SEINO, Hideki AWATA
  • Patent number: 7280071
    Abstract: A satellite-signal reception-processing apparatus for receiving signals, which each have completed a spectrum-spreading process using a spreading code, from a plurality of artificial satellites. Then, on the basis of the received signals, the apparatus computes its own position and velocity. The apparatus includes a position-computation satellite determination section for searching for a set of specific artificial satellites each having its locus known and the time of transmission of its spreading code also known, using this set to compute the position of the apparatus. The apparatus also includes a velocity-computation satellite determination section for searching for a set of particular artificial satellites each having its locus known and the frequency of its carrier determined to be a stable frequency, and using this set to compute the velocity of the apparatus.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: October 9, 2007
    Assignee: Sony Corporation
    Inventor: Hideki Awata
  • Publication number: 20070160117
    Abstract: A satellite signal receiver apparatus by which the hardware scale can be suppressed while high speed synchronization is assured. A carrier frequency component is removed from a satellite signal. Then, adding those of signals obtained after every period interval of spread spectrum codes and signals stored in a memory which have a same phase at the period intervals and writing an addition result back into the memory are repeated by a number of times corresponding to plural periods thereby to accumulate signals corresponding to sums of the signals added over the plural periods at the period intervals into the memory. Then, correlation calculation is performed between the signals for the one period of the spread spectrum codes corresponding to the plural periods and a spread spectrum code of the receiver side to detect a correlation point between the satellite signal and the receiver side spread spectrum code.
    Type: Application
    Filed: October 23, 2006
    Publication date: July 12, 2007
    Inventors: Manabu Nitta, Hideki Awata, Hideki Takahashi
  • Patent number: 7053827
    Abstract: The present invention is intended to provide the synchronization acquisition of signals received from four GPS satellites in a short time and with stability by the time in which an intermediate frequency carrier error of good accuracy can be obtained at the time of power-on sequence, for example. Prerequisites are that at least one GPS satellite signal be in the synchronization hold state, its intermediate frequency carrier frequency be known, the orbit information about that GPS satellite be stored in a storage section, and the position and current time of the GPS receiver be known. Under these prerequisites, an intermediate frequency carrier error is computed from the intermediate frequency carrier frequency, the position and velocity of the GPS satellite obtained from the orbit information and the current time, and the position of the GPS receiver. The intermediate frequency carrier frequency is corrected by the computed intermediate frequency carrier error.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: May 30, 2006
    Assignee: Sony Corporation
    Inventor: Hideki Awata
  • Publication number: 20060022868
    Abstract: The present invention provides a satellite-signal reception-processing apparatus for receiving signals, which each have completed a spectrum-spreading process using a spreading code, from a plurality of artificial satellites. Then, on the basis of the received signals, the apparatus computes its own position and velocity. The apparatus includes a position-computation satellite determination section for carrying out an operation to search the artificial satellites for a set of specific artificial satellites each having its locus already known and the time of transmission of its spreading code also already known as well and designating the set found in the search operation as a set of position-computation artificial satellites to be used in computation of the position of the apparatus.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventor: Hideki Awata
  • Publication number: 20050168382
    Abstract: The present invention is intended to provide the synchronization acquisition of signals received from four GPS satellites in a short time and with stability by the time in which an intermediate frequency carrier error of good accuracy can be obtained at the time of power-on sequence, for example. Prerequisites are that at least one GPS satellite signal be in the synchronization hold state, its intermediate frequency carrier frequency be known, the orbit information about that GPS satellite be stored in a storage section, and the position and current time of the GPS receiver be known. Under these prerequisites, an intermediate frequency carrier error is computed from the intermediate frequency carrier frequency, the position and velocity of the GPS satellite obtained from the orbit information and the current time, and the position of the GPS receiver. The intermediate frequency carrier frequency is corrected by the computed intermediate frequency carrier error.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 4, 2005
    Inventor: Hideki Awata
  • Patent number: 6772065
    Abstract: A GPS receiver that is capable of acquiring a GPS signal from a plurality of GPS satellites efficiently and at a high speed, and that is capable of performing a positioning calculation with a high degree of accuracy. The FFT processing result of the addition result from the PN code, stored in the memory, is multiplied by the FFT processing result of the IF data (the received data), stored in the memory, and by inverse-diffusing this result, a correlative value is obtained. By repeating this process while changing the combination of the PN codes to be added, and the synchronization acquisition processing, by a plurality of PN codes, is performed quickly with only a small amount of processing based on these results.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 3, 2004
    Assignee: Sony Corporation
    Inventors: Jason Sanmiya, Masayuki Takada, Katsuyuki Tanaka, Manabu Nitta, Hideki Awata, Koichiro Teranishi
  • Patent number: 6762715
    Abstract: The at least five simultaneous equations include at least five unknown quantities, namely, a reference time, an error of a clock for measuring a diffusion-code reception time for each of the satellites and the 3-dimensional coordinates of the receiver. The diffusion code is transmitted from each of the satellites at a diffusion-code transmission time expressed as a sum of a time having a value represented by digits expressing a number equal to or greater than one unitary time corresponding to one period of the diffusion code and a time having a value represented by digits expressing a number smaller than the unitary time. The time represented by the digits expressing a number equal to or greater than the unitary time is represented by a sum of the reference time which is a time common to all the satellites and the differential time which varies from satellite to satellite.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: July 13, 2004
    Assignee: Sony Corporation
    Inventors: Hideki Awata, Masayuki Takada