Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.

Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.

Abstract: Polymer of parylene is desirable for an inter-level insulating layer because of a small dielectric constant; however, dimer/monomer of parylene is taken into a polymer layer during the deposition, residual dimer/monomer produces outgas during deposition of silicon oxide over the polymer layer, and the silicon oxide layer tends to peel off from the polymer layer; in order to prevent the resultant semiconductor structure layer from peeling of the silicon oxide layer, the polymer layer is annealed before the deposition of the silicon oxide for previously releasing the residual dimer/monomer from the polymer layer.

Abstract: A polymer of parylene is desirable as an inter-level insulating layer in semiconductor circuits because of its small dielectric constant. However, dimers and monomers of parylene in the source gas are taken into the deposited polymer layer during the deposition. These residual dimers and monomers outgas during the deposition of silicon oxide over the polymer layer, which tends to result in peeling from the polymer layer. In order to prevent the silicon dioxide layer from peeling from the resultant semiconductor structure, the polymer layer is annealed before deposition of the silicon oxide for first releasing the residual dimers and monomers from the polymer layer.

Abstract: In a chemical vapor deposition apparatus in which a liquid raw material is vaporized by bubbling and the vaporized material is used as a raw material gas, an orifice is provided in a pipe between a reaction unit (a dispersion head) and a vaporizing unit (a bubbler), whereby the pressure in the vaporizing unit is controlled so that it is made higher than that in the reaction unit. Instability of the pressure in the vaporizing unit which occurs in the initial phase of film formation is eliminated so that the film formation can be stably performed.

Abstract: A semiconductor device including a first wiring layer, and insulator layer formed on the first wiring layer and including a first silicon oxide film, a spin-coated insulating film formed on the first silicon oxide film and a second silicon oxide film formed on the spin-coated insulating film, a through-hole selectively formed in the insulator layer to expose a part of the first wiring layer, and a second wiring layer formed on the insulator layer and in contact with the part of the first wiring layer exposed through the through-hole, wherein the second silicon oxide film has a density lower than the density of the first silicon oxide film and allows gas from the spin-coated insulating film to go through the second silicon oxide film.

Abstract: Disclosed herein is a semiconductor device having an aluminum wiring formed on a semiconductor substrate and a silicon oxynitride film covering the aluminum wiring and having Si, N, O as main elements, atomic ratio of the three elements being expressed by Si.sub.x N.sub.y O.sub.z (where x+y+z=1.00), a range of the atomic ratio lying on lines interconnecting the following eight points in a Si-N-O ternary system or lying inside a region bounded by these lines;(x=0.51, y=0.28, z=0.21)(x=0.47, y=0.28, z=0.25)(x=0.44, y=0.31, z=0.25)(x=0.41, y=0.36, z=0.23)(x=0.41, y=0.39, z=0.20)(x=0.44, y=0.38, z=0.18)(x=0.46, y=0.37, z=0.17)(x=0.51, y=0.32, z=0.17).Preferably, this silicon oxynitride film contains H of 5 to 18 atomic percents.