Abstract: A tester includes a performance board unit on which a probe card for testing a semiconductor circuit is mounted, and a main body unit to which the performance board unit is detachably attached, in which the performance board unit has a caster on a side closer to the main body unit, and the main body unit has the caster rail supporting the caster and the lifting unit that raises and lowers the caster rail in an attachment/detachment direction of the performance board unit.

Abstract: A tester includes a plurality of slots which extend in a top-bottom direction provided, a card guide having a groove into which a side edge of circuit board units is inserted, a guide block located above the card guide, and overlaps a plurality of the card guides as seen from above and extends along an arrangement direction of the circuit board unit. The guide block exposes the groove for each of the card guides as seen from above, and has recesses for each card guide along with a circuit board unit temporary placement surface which is located between adjacent recesses as seen from above, and onto which the circuit board unit is temporarily placed provided.

Abstract: A semiconductor testing device that includes an under base unit, an under base plate, a floating plate that is connected to an under base unit connector, and is movable on the under base plate towards a mounting direction of a circuit board connector with respect to the under base unit connector, and a coil spring that is elastically deformable, and is interposed between the under base plate and the floating plate in a the mounting direction.

Abstract: A tester includes a performance board unit on which a device under test for testing a semiconductor circuit is mounted, a plurality of board units electrically connected to the device under test via the performance board unit, and a main body unit having an accommodating portion in which the plurality of board units are accommodated, in which the performance board unit is detachably attached to the main body unit with an opening of the accommodating portion closed.

Abstract: A semiconductor testing device includes a main body housing, a plurality of circuit board units inserted and installed inside the main body housing, and an incorrect insertion prevention mechanism having a shape that corresponds to each type of circuit board unit out of the circuit board units, and restricts the circuit board units from being inserted into an incorrect location in the main body housing. The incorrect insertion prevention mechanism includes a pin unit which includes a pin which is disposed in a location that corresponds to the type of the circuit board unit, and a pin receptacle plate having a pin receptacle hole provided in a location where the pin of the pin unit is insertable. The pin unit is installed on a first side of the main body housing and the circuit board unit, while the pin receptacle plate is installed on a second side of the main body housing and the circuit board unit.

Abstract: A tester includes a performance board unit on which a probe card is mounted, a plurality of board units electrically connected to the probe card via the performance board unit, a plurality of power supply units supplying power to the plurality of board units, and a main body unit, on which the performance board unit is mounted, including a first accommodating portion that accommodates the plurality of board units and a second accommodating portion that accommodates the plurality of power supply units, in which the plurality of power supply units are detachably attached to the second accommodating portion, and the main body unit includes a bus bar electrically connected to the plurality of power supply units in an attachment/detachment direction (Y-axis direction) of the plurality of power supply units with respect to the second accommodating portion.

Abstract: An inspection apparatus includes: a wafer fixing mechanism unit configured to support a wafer including a device under test having an electrode terminal on one surface and an optical input/output unit on the other surface; an optical probe provided on the one surface side of the wafer, and configured to transmit/receive an optical signal to/from the optical input/output units of the device under test; a conductive probe provided on the other surface side of the wafer, and electrically contacted with the electrode terminal of the device under test; and a wafer non-contact state maintaining unit which is a planar member having an opening in a center portion, and configured to maintain a distance from the wafer by intaking/exhausting pressurized air with respect to the wafer and to enable access to the device under test on the wafer through the opening.

Abstract: A method for producing a plasma display comprises the step of continuously applying a phosphor paste containing a phosphor powder and an organic compound onto a substrate with a plurality of barrier ribs, from a paste applicator with a plurality of outlet holes. A method for producing a plasma display comprises the steps of coating a substrate with a plurality of baffler ribs, with three phosphor pastes respectively containing a phosphor powder emitting light of red, green or blue, as stripes in the spaces between the respectively adjacent baffler ribs on the substrate, from a paste applicator with outlet holes, and heating to form a phosphor layer.

Abstract: A die, having multiple discharge orifices arrayed in a generally straight line for applying an application fluid to an object of application, and an internal application fluid reservoir, wherein braces are provided in the application fluid reservoir and extending in a direction generally orthogonal to the direction of the array of the discharge orifices. Also, an application apparatus and method for application fluid, for relatively moving a base material wherein stripe-shaped vertical barrier ribs are formed on the surface of the base material and horizontal barrier ribs having a height equal to or lower than the vertical barrier ribs are formed in a direction generally orthogonal to the vertical barrier ribs, and a die provided facing the base material, while discharging application fluid from multiple discharge orifices provided on the die, thereby applying application fluid to selected grooves between the vertical barrier ribs of the base material.

Abstract: A die, having multiple discharge orifices arrayed in a generally straight line for applying an application fluid to an object of application, and an internal application fluid reservoir, wherein braces are provided in the application fluid reservoir and extending in a direction generally orthogonal to the direction of the array of the discharge orifices. Also, an application apparatus and method for application fluid, for relatively moving a base material wherein stripe-shaped vertical barrier ribs are formed on the surface of the base material and horizontal barrier ribs having a height equal to or lower than the vertical barrier ribs are formed in a direction generally orthogonal to the vertical barrier ribs, and a die provided facing the base material, while discharging application fluid from multiple discharge orifices provided on the die, thereby applying application fluid to selected grooves between the vertical barrier ribs of the base material.

Abstract: Since a widely applicable high quality plasma display equipped with a phosphor layer suitable as a highly precise plasma display can be produced continuously at a high productivity level, an industrially advantageous method and apparatus for producing a plasma display can be provided. The highly precise plasma display obtained in the present invention can be widely used in the display field, for example, for wall mounted television sets, information displays, etc.

Abstract: A MOS TFT includes a back gate electrode of a silicide formed on an underlying insulating layer, and a polysilicon layer deposited on the underlying insulating layer so as to completely cover the back gate electrode. A gate oxide and a gate electrode are formed on the polysilicon layer in the named order and positioned above the back gate electrode. In alignment with the gate oxide and the gate electrode, a pair of high concentration source/drain regions are formed in the polysilicon layer, so that a channel is formed by a portion of the polysilicon layer under the gate oxide. The whole is coated with a CVD oxide silicon protection film, and a source/drain electrode is formed to contact to each of the source/drain regions through a contact hole formed through the oxide silicon protection film. By fixing a potential of the back gate, a source-drain breakdown voltage can be considerably increased.

Abstract: A method and an apparatus for displaying a two-dementional tone picture of analysis data by use of the Finite-Element-Method include, in one element, determining lines for a display region on the basis of one tone boundary value of the analysis data and painting the display region with a predetermined color according to the tone boundary value. The operations of determining the boundary lines and painting are repeatedly executed in turn through all of the tone boundary values so as to complete the display of a two-dimensional tone picture in one element. Thereafter, this execution of one element is repeated through all of the finite elements so as to complete the display of a two-dimensional tone picture of an entire display region. As a result, a correct display is obtained on the basis of all optional tone boundary values as well as all optional data values with a convenient visual comprehension of optional analysis data.

Abstract: A lifting mechanism including a carriage mounting a circuit breaker, a disconnecting switch and the like and supported on guide rails to facilitate racking movement of the circuit breaker, disconnecting switch and the like between the positions of electrical engagement and disengagement. The carriage includes a bucket upon which is mounted electrical devices, e.g. a circuit breaker, a disconnecting switch and rollers to transfer a bucket which moves along the guide rails which are detachably engaged in an electrical switchboard.