Patents by Inventor Hideki Imai

Hideki Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200313032
    Abstract: A light emitting device includes a substrate, and a laminated structure provided on the substrate, wherein the laminated structure has a plurality of columnar portions, the columnar portion contains a material having a wurtzite-type crystal structure, in a plan view as seen from a layered direction of the laminated structure, the plurality of columnar portions are arranged in a square lattice form or rectangular lattice form, a line passing through centers of the adjacent columnar portions is inclined relative to m-planes of the columnar portions located between the centers of the adjacent columnar portions, and vertices of the adjacent columnar portions are not placed on the line.
    Type: Application
    Filed: March 31, 2020
    Publication date: October 1, 2020
    Inventors: Yasutaka IMAI, Tetsuji FUJITA, Koichiro AKASAKA, Hideki HAHIRO
  • Publication number: 20200275547
    Abstract: A magneto-optical trap apparatus includes a vacuum vessel for encapsulating an atom to be trapped, an anti-Helmholtz coil for applying a magnetic field to an inside of the vacuum vessel, a laser device for generating a laser beam, and an irradiation device for irradiating the generated laser beam from a plurality of directions. The laser beam includes a first laser beam detuned from a first resonance frequency when the atom transits from a total angular momentum quantum number F in a ground state to a total angular momentum quantum number F?=F+1 in an excited state, and a second laser beam detuned from a second resonance frequency when the atom transits from the total angular momentum quantum number F in the ground state to a total angular momentum quantum number F?=F?1 in the excited state, among transitions from J=0 in a ground state to J?=1 in an excited state.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 27, 2020
    Inventors: Hiromitsu IMAI, Tomoyo AKATSUKA, Katsuya OGURI, Atsushi ISHIZAWA, Hideki GOTOH, Hidetoshi KATORI, Masao TAKAMOTO
  • Publication number: 20200273908
    Abstract: A method of manufacturing a light source device includes the steps of providing a mask layer to a substrate, providing the mask layer with a plurality of first openings and at least one second opening, and growing columnar parts having a light emitting section from the plurality of first openings, and growing a structure from the second opening.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Inventors: Tetsuji Fujita, Yasutaka Imai, Koichiro Akasaka, Hideki Hahiro, Michifumi Nagawa
  • Patent number: 10756116
    Abstract: An active matrix substrate includes a gate metal layer including a plurality of gate bus lines, and a thin film transistor arranged in each pixel region, wherein: the thin film transistor includes a gate electrode, an oxide semiconductor layer arranged on the gate electrode with a gate insulating layer interposed therebetween, wherein the gate electrode is formed in the gate metal layer and is electrically connected to a corresponding one of the plurality of gate bus lines, the gate metal layer has a layered structure including a copper alloy layer and a copper layer arranged on the copper alloy layer, wherein the copper alloy layer is of a copper alloy including Cu and at least one additive metal element, wherein the additive metal element includes Al, and an Al content of the copper alloy is 2 at % or more and 8 at % or less.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Teruyuki Ueda, Yoshihito Hara, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi, Toshikatsu Itoh
  • Patent number: 10748939
    Abstract: A semiconductor device (100A) is provided with: a gate electrode (3); an oxide semiconductor layer (5); a thin-film transistor (101) including a gate insulating layer (4), a source electrode (7S), and a drain electrode (7D); an inter-layer insulating layer (11) arranged so as to cover the thin-film transistor (101) and come into contact with a channel area (5c) of the thin-film transistor (101); and a transparent electroconductive layer (19) arranged on the inter-layer insulating layer (11), the source electrode (7S) and the drain electrode (7D) each having a copper layer (7a), and the device being further provided with a copper oxide film (8) arranged between the source and drain electrodes and the inter-layer insulating layer (11). The inter-layer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 18, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Tetsuo Kikuchi, Shingo Kawashima, Masahiko Suzuki
  • Patent number: 10741696
    Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 11, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Hajime Imai, Hideki Kitagawa, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara, Tohru Daitoh, Toshikatsu Itoh
  • Patent number: 10743386
    Abstract: A display device includes a pixel including a plurality of sub-pixels. Each of the plurality of sub-pixels includes: a light-emission region; and a non-light-emission region other than the light-emission region. The light-emission region includes one or more effective light-emitting parts in which a first electrode, a light emitting layer, and a second electrode are stacked in order, and a light guide provided on side of the one or more effective light-emitting parts on which light is extracted.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 11, 2020
    Assignee: JOLED INC.
    Inventors: Kaoru Abe, Kazuma Teramoto, Toshiaki Imai, Jiro Yamada, Takahide Ishii, Hideki Kobayashi
  • Patent number: 10727784
    Abstract: In an aggregation system comprising a control apparatus which is provided for each consumer and a server apparatus, the server apparatus calculates, for each of the consumers and as an allocation amount of the consumer, an upper limit value for the power which the consumer inputs from the system or a lower limit value for the power which the consumer is to output to the system, according to a requested power provision amount, and sends the respective control instructions designating the calculated allocation amount of each consumer to the control apparatus of the consumer, and the control apparatuses each control the charging and discharging of the corresponding power apparatus so that the power input from the system is equal to or smaller than the allocation amount designated in the control instruction or so that power equal to or larger than the allocation amount is output to the system.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 28, 2020
    Assignees: HITACHI, LTD., IKS CO., LTD.
    Inventors: Hideki Kobayashi, Kouichi Hiraoka, Mitsumasa Takayama, Jun Takahashi, Yuji Fujiki, Takashi Imai
  • Publication number: 20200227560
    Abstract: A semiconductor device (100) of an embodiment of the present invention includes: a substrate (1); a plurality of TFTs (10) supported by the substrate; and a protecting layer (20) covering the plurality of TFTs. Each of the TFTs is a back channel etch type TFT which includes a gate electrode (2), a gate insulating layer (3), an oxide semiconductor layer (4), a source electrode (5) and a drain electrode (6). The gate electrode includes a tapered portion (TP) defined by a lateral surface (2s) which has a tapered shape. When viewed in a direction normal to a substrate surface, a periphery of the oxide semiconductor layer includes an edge (4e1, 4e2) which extends in a direction intersecting a channel width direction (DW) and which is more internal than an edge of the gate electrode in the channel width direction. The distance from the edge of the oxide semiconductor layer to an inside end of the tapered portion is not less than 1.5 ?m.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 16, 2020
    Inventors: Toshikatsu ITOH, Hajime IMAI, Hideki KITAGAWA, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Tohru DAITOH, Masahiko SUZUKI
  • Patent number: 10710768
    Abstract: A pallet includes at least one top board on which a load is to be placed and at least one substantially plate-shaped stringer board that is provided independently of the top board and that has at least one non-contact portion, which is not in contact with the top board in a region between the stringer board and the top board, the stringer board being in contact with the top board in a vertical direction.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 14, 2020
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Shigeru Tsukada, Toshihiro Osawa, Kyoichi Imon, Taisuke Endo, Yusuke Kabe, Satoko Imai, Hideki Yamamoto
  • Patent number: 10700210
    Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 30, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Masahiko Suzuki, Shingo Kawashima, Tohru Daitoh
  • Publication number: 20200185425
    Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interp
    Type: Application
    Filed: May 11, 2018
    Publication date: June 11, 2020
    Inventors: Kengo HARA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Hideki KITAGAWA, Teruyuki UEDA, Masahiko SUZUKI, Setsuji NISHIMIYA, Toshikatsu ITOH
  • Publication number: 20200183208
    Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).
    Type: Application
    Filed: March 13, 2017
    Publication date: June 11, 2020
    Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Hajime IMAI, Toshikatsu ITOH, Hisao OCHI, Hideki KITAGAWA, Masahiko SUZUKI, Teruyuki UEDA, Ryosuke GUNJI, Kengo HARA, Setsuji NISHIMIYA
  • Patent number: 10649293
    Abstract: A display panel includes a substrate, pixel electrodes, switching components, an electrode, a line, a terminal, an insulating film, and a conductive film. The switching components are disposed in a layer lower than the pixel electrodes. The electrode is disposed in a layer different from a layer in which the pixel electrodes are disposed. The line includes sections disposed in a layer lower than the switching components in a display area. The terminal is disposed in a layer upper than the line in a non-display area. The insulating film includes a section disposed between the line and the switching components in the display area and a section disposed between the terminal and the substrate in the non-display area. The conductive film is disposed on the insulating film in a layer between the line and the terminal to connect the line to the terminal.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: May 12, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Yoshihito Hara, Masaki Maeda, Toshikatsu Itoh, Tatsuya Kawasaki
  • Patent number: 10620468
    Abstract: A method of manufacturing a display panel substrate includes a transparent conductive film formation step of forming a transparent conductive film on a flattening film that covers a switching component disposed on a substrate, a metallic film formation step of forming a metallic film so as to cover the transparent conductive film after the transparent conductive film formation step, a line formation step of forming a line by etching the metallic film after the metallic film formation step, and a transparent electrode formation step of forming a transparent electrode that is connected to the line by etching the transparent conductive film after the wire formation step.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: April 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Toshikatsu Itoh, Tohru Daitoh, Hajime Imai, Masaki Maeda, Hideki Kitagawa, Yoshihito Hara, Tatsuya Kawasaki
  • Publication number: 20200111433
    Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
    Type: Application
    Filed: March 16, 2018
    Publication date: April 9, 2020
    Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
  • Publication number: 20200073427
    Abstract: A hybrid power conditioning system manages, as a control target, a plurality of electric power units having different response speeds of charge or discharge, and respectively controls a charge or a discharge of the control target and an input/output of power, to and from a system, based on the charge or the discharge of the control target. A server apparatus generates a control order related to a demand response to the hybrid power conditioning system and calculates an allocation amount of each of the users according to at least an amount of power to be procured. The control order includes the calculated allocation amount and a control mode prescribing a discharge source or a charge destination when a triggering condition is satisfied. Upon receiving the control order, each of the hybrid power conditioning systems activates the control targets in order from the control target having a fastest response speed.
    Type: Application
    Filed: March 19, 2018
    Publication date: March 5, 2020
    Inventors: Hideki KOBAYASHI, Mitsumasa TAKAYAMA, Kouichi HIRAOKA, Yuji FUJIKI, Takashi IMAI
  • Publication number: 20200073155
    Abstract: An electronic component board includes a conductive film, an insulating film, and a transparent electrode film. The insulating film is disposed in a layer upper than the conductive film to cover a side surface and an upper surface of the conductive film. The transparent electrode film is disposed in a layer upper than the insulating film. The transparent electrode film includes an electrode portion and a covering portion. The electrode portion includes an electrode. The electrode portion is electrically connected to the conductive film. The covering portion is separated from the electrode portion and electrically insulated from the conductive film and the electrode portion to overlap the conductive film and the insulating film that covers the conductive film.
    Type: Application
    Filed: August 8, 2019
    Publication date: March 5, 2020
    Inventors: Hideki KITAGAWA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Hajime IMAI, Tohru DAITOH
  • Publication number: 20200066251
    Abstract: A message management unit receives and accumulates a message, wherein the message is distributed for every update, is the message data representing a latest situation of a competition, an explanation generation unit generates an explanatory text for conveying unconveyed information detected from the message, based on conveyed information, a speech synthesis unit outputs a speech converted from the explanatory text, wherein the explanation generation unit stores the unconveyed information for the explanatory text as the conveyed information, stands by until completion of completion of the speech, and initiates a procedure for generating a new explanatory text based on updated unconveyed information.
    Type: Application
    Filed: May 23, 2018
    Publication date: February 27, 2020
    Applicants: NIPPON HOSO KYOKAI, NHK Engineering System, Inc.
    Inventors: Tadashi KUMANO, Ichiro YAMADA, Atsushi IMAI, Hideki SUMIYOSHI, Yuko YAMANOUCHI, Toshihiro SHIMIZU, Nobumasa SEIYAMA, Shoei SATO, Reiko SAITO, Taro MIYAZAKI, Kiyoshi KURIHARA, Manon ICHIKI, Tohru TAKAGI
  • Patent number: D898675
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 13, 2020
    Assignee: SONY CORPORATION
    Inventors: Hideki Imai, Isao Soma, Kazuyoshi Takemura