Abstract: In addition to a main monitor/control module, sub-monitor/control modules are provided, which monitor the operating conditions of transmission sections in real time through a CPU bus. The main monitor/control module collects monitor data from each sub-monitor/control module at a given timing through a LAN and processes the monitor data collected.

Abstract: When the data bus is cut off from the CPU (1) and the transmission ready signal (TXRDY) is activated, the DMA control circuit (10) reads 32 bits of data at once according to the lead address of the destined area for storage in the DRAM (2) and the address width that are set by the CPU (1), and stores the data in the transmission buffer (16). The selector (17) selects 8 bits of data at a time from the transmission buffer (16), the data is written to the communication circuit (14) and thus output, the bus release request is cancelled, 8 bits of data is read at a time from transmission buffer (16), and the data is written into the communication circuit (14). When the transmission ready signal is provided once again, the above-described processing is repeated.

Abstract: In addition to a main monitor/control module, sub-monitor/control modules are provided, which monitor the operating conditions of transmission sections in real time through a CPU bus. The main monitor/control module collects monitor data from each sub-monitor/control module at a given timing through a LAN and processes the monitor data collected.

Abstract: In a frame synchronization circuit, a serial data signal, which includes a frame synchronization code constituted by an M number of bits in one frame, is converted by a serial/parallel converting circuit to a parallel data signal of a 2M-1 number of bits. An M number of pattern detectors of a first synchronization detecting circuit detect the code pattern of the first block of the frame synchronization code from the parallel data signal. A selection signal generating circuit holds outputs of the pattern detectors, and outputs them as a selection signal designating the bit position allotted to the pattern detector which detects the synchronization code pattern. An output of the serial/parallel converting circuit is delayed by a time required for the above-mentioned processing, and supplied to a selector, which selectively outputs an M-bit data signal corresponding to the bit position designated by the selection signal.