Abstract: A simulation coverage calculating apparatus is provided for calculating a simulation coverage for a complete verification. The apparatus includes a first input unit, a second input unit, an effective test pattern calculating unit, a coverage ratio calculating unit, and an output unit. The first input unit reads a property that represents effective test patterns to a logic circuit to be verified. The effective test pattern calculating unit calculates the effective test patterns based on the property. The second input unit reads the test patterns entered and executed by a verifier. The coverage ratio calculating unit calculates a coverage ratio from a ratio of the number of the test patterns matched to the effective test patterns to the number of all of the effective test patterns. The output unit outputs the calculated coverage ratio.

Abstract: A simulation coverage calculating apparatus is provided for calculating a simulation coverage for a complete verification. The apparatus includes a first input unit, a second input unit, an effective test pattern calculating unit, a coverage ratio calculating unit, and an output unit. The first input unit reads a property that represents effective test patterns to a logic circuit to be verified. The effective test pattern calculating unit calculates the effective test patterns based on the property. The second input unit reads the test patterns entered and executed by a verifier. The coverage ratio calculating unit calculates a coverage ratio from a ratio of the number of the test patterns matched to the effective test patterns to the number of all of the effective test patterns. The output unit outputs the calculated coverage ratio.

Abstract: A to-be-verified model 21 including a processor 23, a program RAM 24, a data RAM 25, and a peripheral I/O device 26, which are connected to each other through a bus, is described in hardware description language. A test bench 22, which requests interrupt to the processor 23 through the peripheral I/O device 26, is also described in a hardware description language. A test program 14, which includes an interrupt processing routine according to each interrupt factor and a main routine to be processed by the processor 23, is described in assembly language. A command to write the identifying code of interrupt processing routine in a trace memory region RV in the data RAM 25 is inserted in each interrupt processing routine. After simulating the to-be-verified model 21 and the test bench 22, the trace value RV is compared with an expected value EV so as to verify the interrupt routine execution sequence.

Abstract: An analog-to-digital converter includes a sample and hold circuit for sampling and holding an analog input signal, a comparator circuit for comparing the analog input signal held by the sample and hold circuit with an input signal and generating an output signal, a control circuit for generating a digital signal based on the output signal of the comparator circuit, a digital-to-analog converter for converting the digital signal generated from the control circuit into an analog signal and for supplying the analog signal to the comparator circuit as the input signal, and an initial setting circuit for initializing the analog input signal held by the sample and hold circuit and the input signal which is output from the digital-to-analog converter to a reference voltage.

Abstract: In a central processing unit, one write address is made to correspond to a pair of registers, and when an instruction output from an instruction decoder is a data transfer instruction to either one of the above-mentioned pair of registers, the data held in one of the above-mentioned pair of registers is kept to be held in either register of the above-mentioned pair of registers and the data from the internal data bus is transferred to the remaining register of the pair of registers, and in response to a read instruction, data is transferred from each register to the internal data bus without changing the contents of the other register.