Patents by Inventor Hideki Kamimaki

Hideki Kamimaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6484229
    Abstract: A disk storage apparatus includes a logical unit number correspondence memory for storing the correspondence and the logical unit number designated by a host computer and the logical unit number of the disk storage apparatus, a logical unit number conversion program for converting the logical unit number designated by the host computer to the logical unit number of the disk storage apparatus, and a logical unit correspondence setting program for storing the correspondence of the logical unit number designated by the host computer to the logical unit number of the disk storage in the logical unit number correspondence memory thereby, a plurality of host computers sharing at least one disk storage apparatus.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: November 19, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Ichikawa, Kiyoshi Honda, Naoto Matsunami, Hideki Kamimaki, Osamu Kunisaki
  • Publication number: 20020154478
    Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD-ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.
    Type: Application
    Filed: June 25, 2002
    Publication date: October 24, 2002
    Inventors: Hideki Kamimaki, Yukihide Inagaki, Tsuyoshi Nakagawa, Koichi Kimura, Hideaki Gemma, Hitoshi Kawaguchi
  • Publication number: 20020029323
    Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.
    Type: Application
    Filed: October 24, 2001
    Publication date: March 7, 2002
    Inventors: Hitoshi Kawaguchi, Koichi Kimura, Hideki Kamimaki, Takayuki Tamura, Kazushi Kobayashi
  • Patent number: 6330651
    Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 11, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Kawaguchi, Koichi Kimura, Hideki Kamimaki, Takayuki Tamura, Kazushi Kobayashi
  • Publication number: 20010010622
    Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD-ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 2, 2001
    Inventors: Hideki Kamimaki, Yukihide Inagaki, Tsuyoshi Nakagawa, Koichi Kimura, Hideaki Gemma, Hitoshi Kawaguchi
  • Patent number: 6201693
    Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD-ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: March 13, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Kamimaki, Yukihide Inagaki, Tsuyoshi Nakagawa, Koichi Kimura, Hideaki Gemma, Hitoshi Kawaguchi
  • Patent number: 6108716
    Abstract: A keyboard-detachable data processing unit which keeps a display unit stable under any condition. A link mechanism linking a system unit and a display unit comprises a guide which runs from front to back, a slider which swivels along the guide, and a swinging arm with one end on a system unit and the other end at a position between the base and the tip of the display unit, both ends capable of swiveling. The base of the display unit is on the swiveling slider, and the slider crank mechanism is composed of the display unit, slider, and swinging arm. The center of gravity G of the display unit is always within the upper area of the system unit regardless of whether the display unit is opened or closed.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Kimura, Hideaki Genma, Tsuyoshi Nakagawa, Hideki Kamimaki, Kotaro Matsuo
  • Patent number: 6098159
    Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: August 1, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Kawaguchi, Koichi Kimura, Hideki Kamimaki, Takayuki Tamura, Kazushi Kobayashi
  • Patent number: 5867148
    Abstract: An information processing apparatus includes in its body at least a power supply unit, a disk type storage and a printed circuit board arranged in a predetermined order and further has a keyboard unit which can be sandwiched between the display unit and a keyboard unit supporting portion extending from the body by pivotally moving the display unit. A detector for detecting the detachment of the keyboard unit from the body may be provided to restrict the range of pivotal movement of the display unit in accordance with a detection signal of the detector. Further, the display unit may be provided with pilot light emitting portions, thereby making it possible to recognize a condition of the information processing apparatus.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: February 2, 1999
    Assignees: Hitachi, Ltd., Hitachi Video & Information System, Inc.
    Inventors: Hideki Kamimaki, Kiyokazu Nishioka, Koichi Kimura, Takashi Maruyama, Tsuguji Tachiuchi, Koichi Isaji, Tsuyoshi Nakagawa, Nobuo Tsuchiya, Yoshiyuki Amano, Taisuke Kashima, Akira Takahashi, Tadashi Kyoda, Ryooichi Mizuno
  • Patent number: 5828871
    Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: October 27, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Kawaguchi, Koichi Kimura, Hideki Kamimaki, Takayuki Tamura, Kazushi Kobayashi
  • Patent number: 5812859
    Abstract: An information processing apparatus having a work suspend/resume function which allows operator to use a main memory shared by different processings even when work suspension information is saved therein. A system for allowing a same operational environment as that set up in one information processing apparatus to be easily implemented in another information processing apparatus. A main memory used by a CPU for execution of processings has a function for storing information concerning the state of the information processing apparatus prevailing at a time point when execution of a given processing is suspended by a CPU for allowing the suspended processing to be performed in continuation later on. When the suspension state information has already been stored in the main memory by a former user, the suspension state information is transferred to a removable nonvolatile storage device so that the CPU can perform other processing than the suspended one by using the main memory.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: September 22, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Kamimaki, Koichi Isaji, Masatomi Sasaki, Koichi Kimura, Takayuki Tamura, Tsuguji Tachiuchi
  • Patent number: 5511201
    Abstract: A data processing apparatus which includes a display unit and a power supply controller for supplying power to the display unit. The display unit has a display screen and a back light controller. The power supply controller comprises a switch, at least one output line for receiving the power from the switch and for supplying therethrough the power to electronic devices, a delay circuit for receiving the power from the switch and when the switch is turned ON to start supply of the power, for outputting the power after passage of a predetermined time from the start of the power supply, and a second output line for supplying the power from the delay circuit to the back light controller therethrough.
    Type: Grant
    Filed: March 25, 1992
    Date of Patent: April 23, 1996
    Assignees: Hitachi, Ltd., Hitachi Video & Information System, Inc.
    Inventors: Hideki Kamimaki, Kiyokazu Nishioka, Tsuguji Tachiuchi, Nobuo Tsuchiya, Masahiro Jinushi, Hitoshi Sadamitsu, Hiroshi Ito, Takashi Yoshitomi, Koichi Isaji, Takao Ohba
  • Patent number: 5485623
    Abstract: An information processor operating with a battery writes data which exists in a register of a CPU at that time into a predetermined stack area for transfer of an RAM when a suspend command is received in the normal operation state of the processor and shifts to the suspended state that the power supply to the minimum circuit components including the RAM is maintained and the power supply to the other circuit components is stopped. When insufficient power of the battery is detected in the suspended state, the information processor is started temporarily so as to automatically transfer and store the data in the RAM into a storage device using a non-volatile memory device.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: January 16, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiki Kurokawa, Kiyokazu Nishioka, Hideki Kamimaki, Yoshifumi Atarashi
  • Patent number: 5390293
    Abstract: An information processing equipment capable of multicolor display, comprising a CPU; a display memory which stores display information therein; a display unit which displays the display information in multiple colors selected from a predetermined number of colors to-be-developed; a display control circuit which controls transfer of information between the CPU and the display memory, and which regularly reads out the display information stored in the display memory and then sends the read-out display information to the display unit; a mode selector which selects one of at least two modes consisting of a first mode and a second mode, and which produces selection information, wherein the first mode causes the display unit to develop a smaller number of multiple colors and to operate at a lower frequency, while the second mode causes the display unit to develop a large number of multiple colors and to operate at a higher frequency; a clock signal generator which generates a plurality of clock signals of unequal f
    Type: Grant
    Filed: August 17, 1993
    Date of Patent: February 14, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kiyokazu Nishioka, Hideki Kamimaki, Tsutomu Furuhashi, Kohji Takahashi, Bunichi Fujimaki, Koichi Isaji