Abstract: A detection circuit includes: a differential input circuit configured to receive differential input voltages and generate first differential detection currents corresponding to the differential input voltages; a detection current generation circuit configured to form a current mirror circuit with the differential input circuit and generate second differential detection currents corresponding to the first differential detection currents; a detection voltage generation circuit configured to receive the second differential detection currents and generate a detection voltage having a voltage corresponding to the second differential detection currents; and a comparator circuit configured to compare the detection voltage and a reference voltage and output a signal indicating whether or not the differential input voltages are in a voltage state representing a given idle mode.

Abstract: There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

Abstract: A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.

Abstract: In a differential amplifier circuit, a differential amplifier circuit unit includes: first and second transistors provided between a current source circuit and a load circuit, which receives differential input signals at gates to generate differential output signals at drains; and a third transistor connected between sources of the first and second transistors, which receives a control signal at a gate. A replica amplifier circuit unit includes: a voltage generation circuit which generates first and second reference voltages; first and second replica transistors which receives the first and second reference voltages at gates to generate replica output signals at drains; a third replica transistor connected between sources of the first and second replica transistors, which receives the control signal at a gate; and an operational amplifier which generates the control signal according to a difference between at least one of the first and second reference voltages and the replica output signal.

Abstract: A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

Abstract: A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

Abstract: There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit

Abstract: A lighting device control apparatus used in a vehicle which includes a headlight for illuminating a running direction of the vehicle; a first lighting device provided at a side of an external mirror of the vehicle; a second lighting device provided at a front side of the external mirror; and a direction indicator operating device, operated by a driver of the vehicle, for indicating the running direction of the vehicle, wherein the direction indicator operating device controls at least the on/off state of the first lighting device. The apparatus has a lighting device control device for producing a daytime on-state of the second lighting device, according to an on state of the headlight and an operational position of an ignition switch of the vehicle. The second lighting device, conventionally used as a direction indicator, can be used as a daytime running light for improving the visibility in the daytime.

Abstract: A lighting device control apparatus used in a vehicle which includes a headlight for illuminating a running direction of the vehicle; a first lighting device provided at a side of an external mirror of the vehicle; a second lighting device provided at a front side of the external mirror; and a direction indicator operating device, operated by a driver of the vehicle, for indicating the running direction of the vehicle, wherein the direction indicator operating device controls at least the on/off state of the first lighting device. The apparatus has a lighting device control device for producing a daytime on-state of the second lighting device, according to an on state of the headlight and an operational position of an ignition switch of the vehicle. The second lighting device, conventionally used as a direction indicator, can be used as a daytime running light for improving the visibility in the daytime.

Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Abstract: In block connectors, a male block connector 10 includes male units 11 stacked together in four rows, and six cavities 15, where male metal terminals 2 are received, are formed in each the male units, and are arranged horizontally. Two adjacent male units are combined by a dovetail groove 18 and a dovetail projection 19 provided at these male units. A female block connector 30 includes six female units 31 stacked together horizontally, and four cavities 35, where female metal terminals 5 are received are formed in each of the female units, and are arranged vertically. Two adjacent female units are combined together by retaining plates 39, formed on upper and lower surfaces, and retaining projections 38 formed on the upper and lower surfaces t. Four female metal terminals 5, received in one female unit 31, are connected to male metal terminals 2 received in the male units 11.

Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Abstract: In block connectors, a male block connector 10 includes male units 11 stacked together in four rows, and six cavities 15, where male metal terminals 2 are received, are formed in each the male units, and are arranged horizontally. Two adjacent male units are combined by a dovetail groove 18 and a dovetail projection 19 provided at these male units. A female block connector 30 includes six female units 31 stacked together horizontally, and four cavities 35, where female metal terminals 5 are received are formed in each of the female units, and are arranged vertically. Two adjacent female units are combined together by retaining plates 39, formed on upper and lower surfaces, and retaining projections 38 formed on the upper and lower surfaces t. Four female metal terminals 5, received in one female unit 31, are connected to male metal terminals 2 received in the male units 11.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A semiconductor integrated circuit device has a data holding section for storing information, a counter for counting the number of externally applied pulses, and a comparison/verification section. The comparison/verification section compares an output of the counter with an output of the data holding section, and verifies whether the outputs match or not. This configuration serves to reduce the number of wiring lines formed from pads to a comparison/verification circuit (a signature circuit), and thereby achieves a reduction in layout area and facilitates efficient layout work.