Abstract: An LCD device includes a display panel having a plurality of pixels on which an image is displayed and a timing controller, which includes a receiver receiving image data in series for displaying the image on the display panel wherein the image data being made up of pixel data of three prime colors that are Red, Green and Blue for each pixel, a serial/parallel converter sorting the image data received at the receiver in the order that the display panel can display the image, a sub-pixel generator generating complementary color image data, which are image data of the complementary color indicating the image indicated by the sorted image data, based on information of the sorted image data, and a transmitter transmitting the sorted image data and the complementary color image data.

Abstract: A color display device has a display screen having pixels arrayed, each of which is composed of primary color sub-pixels capable of reproducing respective primary colors and at least one subsidiary color sub-pixel capable of reproducing gray. While gradation signals are generated and supplied to the primary color sub-pixels on the basis of the primary color components of an image to be displayed, the gradation signal to be supplied to the subsidiary color sub-pixel is generated on the basis of the intensity component of the image. The color display device is attained in which the number of gradation levels can be substantially increased without increasing the number of gradation levels of the primary colors.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

Abstract: A liquid crystal display (LCD) device and an apparatus for controlling a liquid crystal display which can perform luminance adjustment no matter what illumination method is employed are provided. An image display screen is divided into a plurality of small regions, and a plurality of counter electrodes 26 are provided for the respective small regions such that the counter electrodes are arranged at positions opposing pixel electrodes with a liquid crystal layer therebetween. When the LCD displays an image, each dimming processor 36 obtains a brightness value of an image in an associated small region based on image data of the image to be displayed, obtains a common-line signal potential to be supplied to the associated counter electrode according to the obtained brightness value, and generates and supplies a correction signal according to the potential to a buffer circuit 40 associated with the counter electrode concerned.

Abstract: An amplifier for amplifying a reception signal, having an input terminal for inputting the reception signal from an antenna, has a grounded gate transistor of which gate is grounded in a high frequency manner and of which source is connected to the input terminal, a load element disposed between the drain of the transistor and a power supply, an output terminal connected to a connection node between the drain and the load element, and an attenuator selectively inserted between the drain and the output terminal.

Abstract: A color display device has a display screen having pixels arrayed, each of which is composed of primary color sub-pixels capable of reproducing respective primary colors and at least one subsidiary color sub-pixel capable of reproducing gray. While gradation signals are generated and supplied to the primary color sub-pixels on the basis of the primary color components of an image to be displayed, the gradation signal to be supplied to the subsidiary color sub-pixel is generated on the basis of the intensity component of the image. The color display device is attained in which the number of gradation levels can be substantially increased without increasing the number of gradation levels of the primary colors.

Abstract: An LCD device includes a display panel having a plurality of pixels on which an image is displayed and a timing controller, which includes a receiver receiving image data in series for displaying the image on the display panel wherein the image data being made up of pixel data of three prime colors that are Red, Green and Blue for each pixel, a serial/parallel converter sorting the image data received at the receiver in the order that the display panel can display the image, a sub-pixel generator generating complementary color image data, which are image data of the complementary color indicating the image indicated by the sorted image data, based on information of the sorted image data, and a transmitter transmitting the sorted image data and the complementary color image data.

Abstract: An LCD device includes a liquid crystal display panel, a receiver, which receives color image data by frame in series, a generator generating gray image data, which are displayable at the liquid crystal display panel, a selector inserting the gray image data as a frame image between two frames of the color image data, which are next to each other on time base and an accelerator increasing a frame rate by which the color and gray image data are transmitted.

Abstract: An amplifier for amplifying a reception signal, having an input terminal for inputting the reception signal from an antenna, has a grounded gate transistor of which gate is grounded in a high frequency manner and of which source is connected to the input terminal, a load element disposed between the drain of the transistor and a power supply, an output terminal connected to a connection node between the drain and the load element, and an attenuator selectively inserted between the drain and the output terminal.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG−Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed.

Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

Abstract: A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.