Abstract: In a communication apparatus, a specific bit is detected from a communication data decoded in a low-speed state of a communication speed. The specific bit is a bit having undergone an inverse change in a logical value. A signal waveform of the communication signal is acquired, which is recorded in a memory and corresponds to the specific bit. Then, a sampling point of the communication signal in a high-speed state of the communication signal is calculated based on (i) the acquired signal waveform and (ii) a logical value of the specific bit.

Abstract: In a communication apparatus, a specific bit is detected from a communication data decoded in a low-speed state of a communication speed. The specific bit is a bit having undergone an inverse change in a logical value. A signal waveform of the communication signal is acquired, which is recorded in a memory and corresponds to the specific bit. Then, a sampling point of the communication signal in a high-speed state of the communication signal is calculated based on (i) the acquired signal waveform and (ii) a logical value of the specific bit.

Abstract: A vehicular communication device is communicable with each of an external communication device disposed outside a vehicle and at least one electronic control device. The vehicular communication device: receives the data from the external communication device and transmits the data to the at least one electronic control device; calculates an estimated power amount for writing the data into the at least one electronic control device; obtains a remaining battery power in a battery; and determines execution or suspension of data transfer.

Abstract: A vehicular communication device is communicable with each of an external communication device disposed outside a vehicle and at least one electronic control device. The vehicular communication device: receives the data from the external communication device and transmits the data to the at least one electronic control device; calculates an estimated power amount for writing the data into the at least one electronic control device; obtains a remaining battery power in a battery; and determines execution or suspension of data transfer.

Abstract: According to an embodiment, a bonding strength test device measures bonding strength between a flexure of a suspension of a hard disk drive and microactuators mounted on a gimbal of the flexure. The bonding strength test device includes a clamp, dummy, and device body. The clamp fixes the flexure. The dummy is adhered to the microactuators. The probe is engaged in the dummy. The device body measures a tensile load applied to the probe while the probe is pulled toward a direction to be apart from the flexure.

Abstract: According to an embodiment, a bonding strength test device measures bonding strength between a flexure of a suspension of a hard disk drive and microactuators mounted on a gimbal of the flexure. The bonding strength test device includes a clamp, dummy, and device body. The clamp fixes the flexure. The dummy is adhered to the microactuators. The probe is engaged in the dummy. The device body measures a tensile load applied to the probe while the probe is pulled toward a direction to be apart from the flexure.

Abstract: Each of nodes in a communication system includes a pull-up circuit connected between a power source and a transmission line and a switching portion connecting and disconnecting the transmission line and a ground line. One of the nodes is a master node, and the others of the nodes are slave nodes. The driver circuits are driven so that the master node constantly outputs the transmission code of logic 1 and the slave node outputting the transmission code of logic 0 extends the width of the low level of the transmission code of logic 1 on the transmission line. The master node further includes a current limiting section limiting an electric current that flows to the transmission line via the pull-up circuit based on at least a signal level of the transmission line.

Abstract: A communication system performs communication using a pulse width modulation code as a transmission code. The communication system includes a plurality of nodes that are connected via a transmission line to be capable of communicating with each other. Each of the nodes including a driver circuit. The driver circuit includes a transistor that enables and blocks conduction between the transmission line and a ground line. The plurality of nodes includes a master node and a slave node. The master node is one of the plurality of nodes. The slave node is at least one node other than the master node among the plurality of nodes. The master node includes a limiter that restricts, when the transistor of the driver circuit is turned off, changes in a conductive state of the transistor.

Abstract: Each of nodes in a communication system includes a pull-up circuit connected between a power source and a transmission line and a switching portion connecting and disconnecting the transmission line and a ground line. One of the nodes is a master node, and the others of the nodes are slave nodes. The driver circuits are driven so that the master node constantly outputs the transmission code of logic 1 and the slave node outputting the transmission code of logic 0 extends the width of the low level of the transmission code of logic 1 on the transmission line. The master node further includes a current limiting section limiting an electric current that flows to the transmission line via the pull-up circuit based on at least a signal level of the transmission line.

Abstract: A transceiver that transmits and receives data used in a communication system, in which the data is encoded by a transmission line code and a signal level of the transmission code changes at a predetermined transition timing in a bit-duration. The transceiver includes: a clock generator that generates an internal clock used for internal circuits; a timing generator that generates, by using the internal clock generated by the clock generator, a timing signal synchronized to a reference clock supplied externally; an encoding circuit that encodes, by using the timing signal generated by the timing generator, a transmission data which is synchronized to the reference clock to be the transmission line code; and a waveform shaping unit that performs a waveform shaping of a waveform at the predetermined transition timing of the transmission data to be based on the reference clock.

Abstract: A decoder for decoding an input signal coded with a pulse width modulation code as a line code to an output signal in a binary code, has a first memory, a first timer, a determination circuit and a first controller. The information on a duty duration of the PWM code, corresponding to at least one kind of the output signals, is stored on the first memory. The first timer has a capacity to measure the duty duration of the input signal. The determination circuit has a capacity to determining which kind of the output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer. The first controller has a capacity to updating the information stored on the first memory, on the basis of the determination result and the measured duty duration.

Abstract: A communication apparatus includes a detecting unit, a process performing unit, and a range setting unit. The detecting unit detects a boundary pattern periodically appearing between codes in a binary coded signal transmitted through a transmission line. The boundary pattern is information showing a boundary appearing between codes. The process performing unit performs a process in synchronization with timing of appearance of the boundary pattern. The range setting unit sets an allowance range which is set include timing at which it is estimated that the next boundary pattern appears. The timing is counted from the timing currently detected by the detecting unit. The detecting unit includes a section which detects the timing of appearance of the boundary pattern during the allowance range.

Abstract: A communication system performs communication using a pulse width modulation code as a transmission code. The communication system includes a plurality of nodes that are connected via a transmission line to be capable of communicating with each other. Each of the nodes including a driver circuit. The driver circuit includes a transistor that enables and blocks conduction between the transmission line and a ground line. The plurality of nodes includes a master node and a slave node. The master node is one of the plurality of nodes. The slave node is at least one node other than the master node among the plurality of nodes. The master node includes a limiter that restricts, when the transistor of the driver circuit is turned off, changes in a conductive state of the transistor.

Abstract: Serial data are transmitted between transceivers via a communication path, each bit expressed by a dominant code or a recessive code which vary between dominant and recessive levels, the dominant code having a greater proportion of duration at the dominant level. A device (clock master) can continuously output successive recessive codes to the communication path, in which condition a transceiver can transmit a dominant code by producing an output drive signal which overwrites a part of a recessive code, currently being received from the communication path, to the dominant level. The output drive signal is shaped with a steeper edge slope at a transition from an inactive to an active level than from the active to the inactive level, enabling an increased data transmission rate without increased noise.

Abstract: In a communication system, a bus allows information to be communicated thereon as signals. Each of the signals has an electrical dominant level thereon and an electrical recessive level thereon. The electrical dominant level is asserted on the bus in priority to the electrical recessive level. Each of a master node and at least one autonomous communicating slave node detects that the bus is in an idle state when the electrical recessive level on the bus is continued for a predetermined period or more, transmits a corresponding header via the bus after detection of the bus being in the idle state, and performs arbitration on the bus based on the corresponding header.

Abstract: In a transceiver, a clock generator generates a second clock synchronized with a first clock. The second clock has a period corresponding to a duration of one bit of a digital signal. When first transmission data is supplied to the transceiver with being asynchronous to the second clock, a sampling timing generator detects start data of the first transmission data as a start timing, and generates sampling timings based on the first clock in response to the start timing. The sampling timings have intervals each of which is defined to correspond to the period of the second clock. The first sampling timing is spaced from the start timing. A sampling module samples, at each of the sampling timings, the first transmission data, thus generating second transmission data synchronized with the second clock.

Abstract: A transceiver that transmits and receives data used in a communication system, in which the data is encoded by a transmission line code and a signal level of the transmission code changes at a predetermined transition timing in a bit-duration. The transceiver includes: a clock generator that generates an internal clock used for internal circuits; a timing generator that generates, by using the internal clock generated by the clock generator, a timing signal synchronized to a reference clock supplied externally; an encoding circuit that encodes, by using the timing signal generated by the timing generator, a transmission data which is synchronized to the reference clock to be the transmission line code; and a waveform shaping unit that performs a waveform shaping of a waveform at the predetermined is transition timing of the transmission data to be based on the reference clock.

Abstract: A communication apparatus includes a detecting unit, a process performing unit, and a range setting unit. The detecting unit detects a boundary pattern periodically appearing between codes in a binary coded signal transmitted through a transmission line. The boundary pattern is information showing a boundary appearing between codes. The process performing unit performs a process in synchronization with timing of appearance of the boundary pattern. The range setting unit sets an allowance range which is set include timing at which it is estimated that the next boundary pattern appears. The timing is counted from the timing currently detected by the detecting unit. The detecting unit includes a section which detects the timing of appearance of the boundary pattern during the allowance range.

Abstract: An encoding circuit encodes a NRZ code into a transmission line code. A decoding circuit decodes the transmission line code into a NRZ code. If an operation-mode specified by a setting signal is a normal-mode, a transmission switching circuit provides transmit-data received from an input terminal to the encoding circuit to output the encoded transmit-data as communication-data from a communication terminal. If the operation-mode is a sleep-mode, the transmission switching circuit outputs the transmit-data received from the input terminal as the communication-data from the communication terminal. If the operation-mode specified by the setting signal is a normal-mode, a reception switching circuit provides the communication-data received from the communication terminal to the decoding circuit to output the decoded communication-data as receive-data from an output terminal.

Abstract: A decoder for decoding an input signal coded with a pulse width modulation code as a line code to an output signal in a binary code, has a first memory, a first timer, a determination circuit and a first controller. The information on a duty duration of the PWM code, corresponding to at least one kind of the output signals, is stored on the first memory. The first timer has a capacity to measure the duty duration of the input signal. The determination circuit has a capacity to determining which kind of the output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer. The first controller has a capacity to updating the information stored on the first memory, on the basis of the determination result and the measured duty duration.