Patents by Inventor Hideki Kawahara

Hideki Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230261417
    Abstract: An object of the present disclosure is to relieve tension applied to a cable. A cable connection device (2) includes a first holder (3), a second holder (4) and a support (5). The first holder (3) is configured to hold a tip part (111) of an end (110) of a first cable (11). The second holder (4) is configured to hold an intermediate part (112) of the end (110). The support (5) is configured to support the first holder (3). The second holder (4) is fixed with respect to a power feed control device body (10). The first holder (3) is supported by the second holder (4) through the support (5) to restrict at least movement of the first cable (11) in a pulling direction of the first cable (11).
    Type: Application
    Filed: May 17, 2021
    Publication date: August 17, 2023
    Inventors: Ryota TOMIYAMA, Hideki KAWAHARA, Hideki OKA, Kouji KAKIUCHI, Mizuki YAGURA, Shinichi NAKAMURA
  • Publication number: 20220415843
    Abstract: A semiconductor device includes a semiconductor element, a conductive member, and solder portions. The semiconductor element includes first main electrodes and a protective film on a first main surface, and a second main electrode on a second main surface. The protective film has an interposed film portion between the first main electrodes. The conductive member has facing portions each facing a corresponding one of the first main electrodes and an interposed conductive portion disposed between the facing portions. The solder portions are disposed between the first main electrodes and the facing portions and separated away from each other by the interposed film portion and the interposed conductive portion to define a space between the solder portions. The interposed film portion and the interposed conductive portion are less likely wetted to the solder portions to avoid the solder portions in liquid phase entering into the space during soldering.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 29, 2022
    Inventor: Hideki KAWAHARA
  • Patent number: 10535577
    Abstract: In a semiconductor device, a plurality of semiconductor chips included in an upper-arm circuit are connected in parallel between a pair of upper-arm plates, while a plurality of semiconductor chips included in a lower-arm circuit are connected in parallel between a pair of lower-arm plates. In each of the arm circuits, the plurality of semiconductor chips are arranged in a direction perpendicular to a direction in which emitter electrodes and pads are arranged, the pads are disposed on the same side of the emitter electrodes, and signal terminals extend in the same direction. A series-connecting part between the upper- and lower-arm circuits includes a joint part 20 continued to respective side surfaces of the corresponding upper- and lower-arm plates. Each of inductances of respective parallel-connecting parts of the upper- and lower-arm plates which connect the semiconductor chips in parallel is smaller than an inductance of the series-connecting part.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 14, 2020
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Ishino, Hideki Kawahara, Shinji Hiramitsu, Shunsuke Arai
  • Patent number: 10367346
    Abstract: The electric leakage protection device (feed control device includes an electric leakage detector, an electric leakage protector, and a self leakage generator. The electric leakage detector outputs an electric leakage detection signal when a current leaked from a main circuit exceeds a threshold value. The electric leakage protector opens a contact device interposed in the main circuit when receiving the electric leakage detection signal. The self leakage generator includes; a first short circuit having a first electric resistance component and a first switch component electrically connected in series with each other, and a second short circuit having a second electric resistance component and a second switch component electrically connected in series with each other. The first short circuit and the second short circuit are electrically connected in parallel with each other with regard to a pair of power supply paths constituting the main circuit.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: July 30, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoki Fukuo, Koji Yamato, Hideki Kawahara
  • Publication number: 20190088568
    Abstract: In a semiconductor device, a plurality of semiconductor chips included in an upper-arm circuit are connected in parallel between a pair of upper-arm plates, while a plurality of semiconductor chips included in a lower-arm circuit are connected in parallel between a pair of lower-arm plates. In each of the arm circuits, the plurality of semiconductor chips are arranged in a direction perpendicular to a direction in which emitter electrodes and pads are arranged, the pads are disposed on the same side of the emitter electrodes, and signal terminals extend in the same direction. A series-connecting part between the upper- and lower-arm circuits includes a joint part 20 continued to respective side surfaces of the corresponding upper- and lower-arm plates. Each of inductances of respective parallel-connecting parts of the upper- and lower-arm plates which connect the semiconductor chips in parallel is smaller than an inductance of the series-connecting part.
    Type: Application
    Filed: April 27, 2017
    Publication date: March 21, 2019
    Inventors: Hiroshi ISHINO, Hideki KAWAHARA, Shinji HIRAMITSU, Shunsuke ARAI
  • Publication number: 20170222424
    Abstract: The electric leakage protection device (feed control device includes an electric leakage detector, an electric leakage protector, and a self leakage generator. The electric leakage detector outputs an electric leakage detection signal when a current leaked from a main circuit exceeds a threshold value. The electric leakage protector opens a contact device interposed in the main circuit when receiving the electric leakage detection signal. The self leakage generator includes; a first short circuit having a first electric resistance component and a first switch component electrically connected in series with each other, and a second short circuit having a second electric resistance component and a second switch component electrically connected in series with each other. The first short circuit and the second short circuit are electrically connected in parallel with each other with regard to a pair of power supply paths constituting the main circuit.
    Type: Application
    Filed: February 26, 2015
    Publication date: August 3, 2017
    Inventors: Naoki FUKUO, Koji YAMATO, Hideki KAWAHARA
  • Patent number: 9373570
    Abstract: A semiconductor module includes: a semiconductor element; first and second main current passages for energizing the semiconductor element, the first and second main current passages being opposed to each other in such a manner that a first energization direction of the first main current passage is opposite to a second energization direction of the second main current passage, or an angle between the first energization direction and the second energization direction is an obtuse angle; and a coil unit sandwiched between the first and second main current passages. The coil unit includes a coil, which generates an induced electromotive force when a magnetic flux interlinks with the coil, the magnetic flux being generated when current flows through the first and second main current passages.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 21, 2016
    Assignee: DENSO CORPORATION
    Inventors: Hideki Kawahara, Takanori Imazawa
  • Patent number: 9213217
    Abstract: Disclosed is an imaging apparatus provided with: a light irradiation unit which irradiates a target area with light; a differential image generation unit which generates a differential image between a first image which was taken in synchronization with the irradiation period during which the light irradiation unit irradiates the light and a second image which was taken outside the irradiation period; a transmittance estimation unit which estimates the light transmittance of an object in the target area; and a light exposure adjustment unit which adjusts the exposure based on the estimation result from the transmittance estimation unit. The transmittance estimation unit estimates the transmittance of the object from at least one of the first image, the second image, and the differential image.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: December 15, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuhiro Mori, Hideki Kawahara, Mutsuhiro Yamanaka, Toshiharu Takenouchi, Eiji Nakamoto, Osamu Uesugi
  • Publication number: 20140346635
    Abstract: A semiconductor module includes: a semiconductor element; first and second main current passages for energizing the semiconductor element, the first and second main current passages being opposed to each other in such a manner that a first energization direction of the first main current passage is opposite to a second energization direction of the second main current passage, or an angle between the first energization direction and the second energization direction is an obtuse angle; and a coil unit sandwiched between the first and second main current passages. The coil unit includes a coil, which generates an induced electromotive force when a magnetic flux interlinks with the coil, the magnetic flux being generated when current flows through the first and second main current passages.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 27, 2014
    Applicant: DENSO CORPORATION
    Inventors: Hideki KAWAHARA, Takanori IMAZAWA
  • Patent number: 8781819
    Abstract: The invention relates to a periodic signal processing method, a periodic signal conversion method, and a periodic signal processing device capable of reducing the influence of periodicity without using a spectral model. Time windows are arranged such that a center of each of the time windows is at a division position which divides a fundamental frequency in a temporal direction into fractions 1/n (where n is an integer equal to or larger than 2) so as to extract a plurality of portions of different ranges from a signal having periodicity. A power spectrum for the plurality of portions extracted by the respective time windows is calculated, and the calculated power spectrum is added with a same ratio.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: July 15, 2014
    Assignee: Wakayama University
    Inventors: Hideki Kawahara, Masanori Morise, Toru Takahashi, Toshio Irino
  • Publication number: 20120320218
    Abstract: Disclosed is an imaging apparatus provided with: a light irradiation unit which irradiates a target area with light; a differential image generation unit which generates a differential image between a first image which was taken in synchronization with the irradiation period during which the light irradiation unit irradiates the light and a second image which was taken outside the irradiation period; a transmittance estimation unit which estimates the light transmittance of an object in the target area; and a light exposure adjustment unit which adjusts the exposure based on the estimation result from the transmittance estimation unit. The transmittance estimation unit estimates the transmittance of the object from at least one of the first image, the second image, and the differential image.
    Type: Application
    Filed: February 23, 2011
    Publication date: December 20, 2012
    Inventors: Yasuhiro Mori, Hideki Kawahara, Mutsuhiro Yamanaka, Toshiharu Takenouchi, Eiji Nakamoto, Osamu Uesugi
  • Patent number: 8212261
    Abstract: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 3, 2012
    Assignee: DENSO CORPORATION
    Inventors: Hiroyuki Ichikawa, Hideki Kawahara, Hiroki Nakamura
  • Publication number: 20110015931
    Abstract: The invention relates to a periodic signal processing method, a periodic signal conversion method, and a periodic signal processing device capable of reducing the influence of periodicity without using a spectral model. Time windows are arranged such that a center of each of the time windows is at a division position which divides a fundamental frequency in a temporal direction into fractions 1/n (where n is an integer equal to or larger than 2) so as to extract a plurality of portions of different ranges from a signal having periodicity. A power spectrum for the plurality of portions extracted by the respective time windows is calculated, and the calculated power spectrum is added with a same ratio.
    Type: Application
    Filed: July 18, 2008
    Publication date: January 20, 2011
    Inventors: Hideki Kawahara, Masanori Morise, Toru Takahashi, Toshio Irino
  • Patent number: 7851382
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed to a carbon layer; annealing the SiC layer to activate the impurity with covering the SiC layer with the carbon layer; removing the carbon layer; and performing a sacrifice oxidation process. The performing the sacrifice oxidation process includes: forming a sacrifice oxide film; and removing the sacrifice oxide film. The forming the oxide film is performed after the performing the sacrifice oxidation process.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 14, 2010
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Nakamura, Hideki Kawahara
  • Patent number: 7645975
    Abstract: A spatial information detecting device for accurately detecting information of a target space is provided. This device has photoelectric converters for receiving a reflection light from the space, in which a flashing light is being irradiated, a charge storage portion formed in each of the photoelectric converters by applying a control voltage to electrodes on each of the photoelectric converters, a controller for controlling the number of electrodes, to which the control voltage is applied, such that an area of the charge storage portion changes based on a flash cycle of the flashing light, and an amplitude-image generator for generating an amplitude image having pixel values, each of which is provided by a difference between electric charges collected in a lighting period of the flashing light by a charge storage portion and the electric charges collected in a non-lighting period of the flashing light by another charge storage portion.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: January 12, 2010
    Assignee: Panasonic Electric Works Co., Ltd.
    Inventors: Hideki Kawahara, Motoo Ikari, Kenichi Hagio, Eiji Nakamoto
  • Publication number: 20080315211
    Abstract: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.
    Type: Application
    Filed: May 13, 2008
    Publication date: December 25, 2008
    Applicant: DENSO CORPORATION
    Inventors: Hiroyuki Ichikawa, Hideki Kawahara, Hiroki Nakamura
  • Publication number: 20080318438
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed to a carbon layer; annealing the SiC layer to activate the impurity with covering the SiC layer with the carbon layer; removing the carbon layer; and performing a sacrifice oxidation process. The performing the sacrifice oxidation process includes: forming a sacrifice oxide film; and removing the sacrifice oxide film. The forming the oxide film is performed after the performing the sacrifice oxidation process.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 25, 2008
    Applicant: DENSO CORPORATION
    Inventors: Hiroki Nakamura, Hideki Kawahara
  • Patent number: D795802
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 29, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Noboru Inagaki, Hideki Kawahara, Shinichi Nakamura, Masahiko Kimura
  • Patent number: D1019768
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: March 26, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Shigeaki Isobe, Manabu Kawahara, Hideki Kato
  • Patent number: D1025204
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 30, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Satoshi Kaminaga, Hideki Kato, Manabu Kawahara