Patents by Inventor Hideki Kitahata

Hideki Kitahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100193373
    Abstract: A method of rear surface treatment is carried out by: preparing a semiconductor device in which an integrated circuit having a plurality of electrodes is provided on the front surface of a semiconductor substrate; electrically connecting the plurality of electrodes to an anode; and electropolishing the rear surface of the semiconductor substrate by performing anodic oxidation with an electrolytic solution placed in contact with the rear surface of the semiconductor substrate.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 5, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: HIDEKI KITAHATA
  • Publication number: 20100193374
    Abstract: A method of rear surface treatment is carried out by: preparing a semiconductor or device in which an integrated circuit having a plurality of electrodes is provided on the front surface of a semiconductor substrate; electrically con netting the plurality of electrodes to an anode; and electropolishing the rear surface of the semiconductor substrate by performing anodic oxidation with an electrolytic solution placed in contact with the rear surface of the semiconductor substrate.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 5, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hideki KITAHATA
  • Patent number: 6686753
    Abstract: In evaluation and analysis of a semiconductor device using optical detection for a semiconductor chip, both front side analysis and back side analysis are enabled at low cost and a short TAT. A prober for conducting the analysis includes a board having a size equal to the size of a semiconductor wafer, a quartz plate provided in an opening of the board, and a manipulator on the board. The semiconductor chip is pushed and fixed onto a quartz plate using the pressure from a probe. During the front side analysis, the prober for conducting the analysis is mounted on a wafer stage and analysis is performed using an optical device while an electrical input is made through the probe. During the back side analysis, a removable plate is attached and the prober for conducting the analysis is turned upside down and mounted on the wafer stage. The analysis is again performed using the optical device while electrical input is made through the probe.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: February 3, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Kitahata
  • Patent number: 6656029
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 2, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Kitahata
  • Patent number: 6608359
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 19, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Kitahata
  • Publication number: 20030000915
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Application
    Filed: August 29, 2002
    Publication date: January 2, 2003
    Applicant: NEC Corporation
    Inventor: Hideki Kitahata
  • Publication number: 20030000917
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Application
    Filed: August 29, 2002
    Publication date: January 2, 2003
    Applicant: NEC Corporation
    Inventor: Hideki Kitahata
  • Patent number: 6475398
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemishperical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: November 5, 2002
    Assignee: NEC Corporation
    Inventor: Hideki Kitahata
  • Publication number: 20020048892
    Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.
    Type: Application
    Filed: November 13, 2001
    Publication date: April 25, 2002
    Applicant: NEC CORPORATION
    Inventor: Hideki Kitahata
  • Publication number: 20020043707
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemishperical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Application
    Filed: September 25, 2001
    Publication date: April 18, 2002
    Applicant: NEC Corporation
    Inventor: Hideki Kitahata
  • Patent number: 6329699
    Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: December 11, 2001
    Assignee: NEC Corporation
    Inventor: Hideki Kitahata
  • Publication number: 20010013635
    Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.
    Type: Application
    Filed: March 23, 1998
    Publication date: August 16, 2001
    Inventor: HIDEKI KITAHATA
  • Patent number: 6080631
    Abstract: In a method for manufacturing a bipolar transistor, a semiconductor layer having a collector region of a first conductivity type is formed, and an epitaxial semiconductor layer of a second conductivity type is grown on the semiconductor layer. Then, impurities are thermally diffused from the epitaxial semiconductor layer into the semiconductor layer. Thus, a base region is formed by the epitaxial semiconductor layer and a part of the semiconductor layer.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: June 27, 2000
    Assignee: NEC Corporation
    Inventor: Hideki Kitahata