Patents by Inventor Hideki KOBA
Hideki KOBA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9722769Abstract: An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit.Type: GrantFiled: February 17, 2016Date of Patent: August 1, 2017Assignee: Hitachi, Ltd.Inventors: Takemasa Komori, Hideki Koba, Junya Nasu
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Publication number: 20170180162Abstract: An adaptive equalizer includes: a speculative equalization circuit which operates a plurality of first tap coefficients with respect to input data and selects operation data corresponding to the input data from a plurality of operation data obtained by the operation; and an adaptive equalization circuit which generates the plurality of first tap coefficients, on the basis of the input data.Type: ApplicationFiled: June 20, 2016Publication date: June 22, 2017Inventors: Hideki KOBA, Keiki WATANABE, Fumio YUKI
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Patent number: 9667454Abstract: An adaptive equalizer includes: a speculative equalization circuit which operates a plurality of first tap coefficients with respect to input data and selects operation data corresponding to the input data from a plurality of operation data obtained by the operation; and an adaptive equalization circuit which generates the plurality of first tap coefficients, on the basis of the input data.Type: GrantFiled: June 20, 2016Date of Patent: May 30, 2017Assignee: Hitachi, Ltd.Inventors: Hideki Koba, Keiki Watanabe, Fumio Yuki
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Publication number: 20170005841Abstract: An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit.Type: ApplicationFiled: February 17, 2016Publication date: January 5, 2017Inventors: Takemasa KOMORI, Hideki KOBA, Junya NASU
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Patent number: 8963637Abstract: A semiconductor device capable of achieving high speed performance in addition to correction of differential offset and a communication device provided with the semiconductor device are provided. For example, there are provided: a variable gain type differential amplifier circuit VGA1 which receives a gain setting signal ASET, which amplifies differential input signals INP and INN by a gain indicated by the gain setting signal, and which outputs differential output signals OUTP? and OTUN?; and an offset correcting circuit unit OFCBK1 which cancels an offset voltage (VOF and VOFO) generated in the VGA1. Here, the OFCBK1 cancels an output offset voltage VOFO (which results in an input offset voltage VOF) by receiving the ASET, generating a correction voltage changed in accordance with the gain, and adding the correction voltage to the OUTP? and OUTN?.Type: GrantFiled: May 23, 2013Date of Patent: February 24, 2015Assignee: Hitachi, LtdInventors: Hideki Koba, Keiki Watanabe, Kouji Fukuda
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Publication number: 20130314158Abstract: A semiconductor device capable of achieving high speed performance in addition to correction of differential offset and a communication device provided with the semiconductor device are provided. For example, there are provided: a variable gain type differential amplifier circuit VGA1 which receives a gain setting signal ASET, which amplifies differential input signals INP and INN by a gain indicated by the gain setting signal, and which outputs differential output signals OUTP? and OTUN?; and an offset correcting circuit unit OFCBK1 which cancels an offset voltage (VOF and VOFO) generated in the VGA1. Here, the OFCBK1 cancels an output offset voltage VOFO (which results in an input offset voltage VOF) by receiving the ASET, generating a correction voltage changed in accordance with the gain, and adding the correction voltage to the OUTP? and OUTN?.Type: ApplicationFiled: May 23, 2013Publication date: November 28, 2013Inventors: Hideki Koba, Keiki Wantanabe, Kouji Fukuda
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Patent number: 8441300Abstract: Power consumption is increased in an interface circuit having a signal processing function for waveform shaping due to influence of a circuit added for waveform shaping. Also, since a plurality of boards are connected to a backplane in a system, they are not exchanged in accordance with distances while there are boards being far or near are mixed, but a common board is used. Thus, it is necessary to prepare a configuration of an interface circuit meeting the longest transfer distance. An interface circuit disabling a part of or all of operations of a waveform shaping circuit is provided. Accordingly, in accordance with transfer distances, switching of operation ranges of waveform shaping circuit inside the interface circuit is possible, and operation ranges of the waveform shaping circuit can be limited, and power consumption of the interface circuit, an LSI including the interface circuit, and a server device can be reduced.Type: GrantFiled: January 26, 2011Date of Patent: May 14, 2013Assignee: Hitachi, Ltd.Inventors: Keiki Watanabe, Takashi Muto, Hideki Koba
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Publication number: 20110181335Abstract: Power consumption is increased in an interface circuit having a signal processing function for waveform shaping due to influence of a circuit added for waveform shaping. Also, since a plurality of boards are connected to a backplane in a system, they are not exchanged in accordance with distances while there are boards being far or near are mixed, but a common board is used. Thus, it is necessary to prepare a configuration of an interface circuit meeting the longest transfer distance. An interface circuit disabling a part of or all of operations of a waveform shaping circuit is provided. Accordingly, in accordance with transfer distances, switching of operation ranges of waveform shaping circuit inside the interface circuit is possible, and operation ranges of the waveform shaping circuit can be limited, and power consumption of the interface circuit, an LSI including the interface circuit, and a server device can be reduced.Type: ApplicationFiled: January 26, 2011Publication date: July 28, 2011Inventors: KEIKI WATANABE, Takashi Muto, Hideki Koba
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Publication number: 20110038426Abstract: In order to optimize with high accuracy parameters that a fast I/F has, optimization by training is required. Regarding these parameters, their optimum values vary to an operating frequency band and a power supply voltage of the I/F. In order to lower the operating frequency band and lower the power supply voltage for reduction of power consumption, re-training that requires a time becomes needed. By obtaining in advance optimum combinations of the operating frequency band, the power supply voltage, and various parameters of the I/F for various parameters of the I/F and then by making a table with them, it is possible to optimize the parameters in a short time by referring to the table in optimizing the power supply voltage. By the optimization of the parameters in a short time being enabled, it is also possible to perform dynamic optimization during an operation of the device.Type: ApplicationFiled: July 12, 2010Publication date: February 17, 2011Inventors: Hideki KOBA, Takashi MUTO