Abstract: Area monitoring system includes a plurality of sensor devices each installed in a monitoring target area and configured to detect a mobile object moving in the monitoring target area and a determiner configured to determine whether or not mobile objects detected by the plurality of sensor devices are the same physical object on the basis of detection results of the plurality of sensor devices. The plurality of sensor devices include at least a radio wave sensor and an optical sensor. The determiner determines whether or not mobile objects detected by the radio wave sensor and the optical sensor are the same physical object on the basis of information of at least one of feature quantities regarding movements of the mobile objects and reflection intensities corresponding to attributes of the mobile objects when the mobile objects have been detected by the radio wave sensor and the optical sensor.

Abstract: According to an embodiment, an area monitoring system includes a sensor device installed at a position where a monitoring target area can be imaged, an analyzer configured to analyze an image captured by the sensor device, a manager configured to manage a situation of the monitoring target area on the basis of an analysis result of the analyzer, and a provider configured to provide information about the monitoring target area. The manager causes the provider to provide information for promoting maintenance regarding at least one of the monitoring target area or the sensor device when a degree of deviation between a state of a road included in the image and a state of the road based on a predetermined reference image of the sensor device is greater than or equal to a threshold value.

Abstract: According to an embodiment, an area monitoring system includes a sensor device installed at a position where a monitoring target area can be imaged, an analyzer configured to analyze an image captured by the sensor device, a manager configured to manage a movement situation of a mobile object moving on a road included in the monitoring target area on the basis of an analysis result of the analyzer, and a provider configured to provide prescribed information to the mobile object. The provider provides an action instruction for the mobile object to the mobile object when the mobile object is likely to depart from the road on the basis of the movement situation.

Abstract: A resin composition for a circuit board, containing a melt-fabricable fluororesin and a particulate boron nitride. The particulate boron nitride has a ratio (b)/(a) of 1.0 or higher, wherein (a) represents a proportion of particles having a particle size of 14.6 to 20.6 ?m and (b) represents a proportion of particles having a particle size of 24.6 to 29.4 ?m. Also disclosed is a molded article for a circuit board obtained from the resin composition, a laminate for a circuit board including a metal layer (A1) and a layer (B) obtained from the resin composition, and a circuit board including a metal layer (A2) and a layer (B) obtained from the resin composition.

Abstract: An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.

Abstract: An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A semiconductor device including a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, a detection circuit that refers to an output voltage of the program voltage supply circuit and detects a decrease of the program voltage supplied thereby, a frequency converting circuit that generates the clock signal by converting a frequency of a clock signal generated by an oscillator circuit into a lower frequency when the program voltage supplied by the program voltage supply circuit becomes equal to or lower than a given voltage, and a voltage generating circuit that generates a voltage supplied to a gate of the memory cell by using a clock signal, the frequency of which is converted by the frequency converting circuit. It is therefore possible to make the best use of the ability of the program voltage generating circuit in programming.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A vacuum deposition system comprises a vacuum vessel, an evaporation source holder located in the vacuum vessel for holding an evaporation source and a holding jig provided in the vacuum vessel for holding a substrate facing the evaporation source. An adhesion-prevention member is located at outer peripheries of the evaporation source and the holding jig along an inner wall of the vacuum vessel. The adhesion-prevention member is spaced from the inner wall of the vacuum vessel. The adhesion-prevention member includes members slanted diagonally downward from the central part toward the inner wall. Thereby, the adhesion-prevention member prevents an evaporant from the evaporation source from adhering to the inner wall of the vacuum vessel. A heater on the adhesion-prevention member heats the adhesion-prevention member to exfoliate particles that are deposited to the adhesion-prevention member.

Abstract: There is provided a semiconductor device including a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, a detection circuit that refers to an output voltage of the program voltage supply circuit and detects a decrease of the program voltage supplied thereby, a frequency converting circuit that generates the clock signal by converting a frequency of a clock signal generated by an oscillator circuit into a lower frequency when the program voltage supplied by the program voltage supply circuit becomes equal to or lower than a given voltage, and a voltage generating circuit that generates a voltage supplied to a gate of the memory cell by using a clock signal, the frequency of which is converted by the frequency converting circuit. It is therefore possible to make the best use of the ability of the program voltage generating circuit in programming.

Abstract: A vacuum deposition system comprises a vacuum vessel, an evaporation source holder provided in the vacuum vessel for holding an evaporation substance and a holding jig provided in the vacuum vessel for holding a substrate facing the evaporation source. An adhesion-prevention member is provided at outer peripheries of the evaporation source and the holding jig along an inner wall of the vacuum vessel across a region from a position facing a lateral part of the evaporation source holder to a position facing a lateral part of the holding jig. The adhesion-prevention member is spaced apart from the inner wall of the vacuum vessel. The adhesion-prevention member includes members slanted diagonally downward from the central part side toward the inner wall. Thereby, the adhesion-prevention member prevents an evaporant from the evaporation source from adhering to the inner wall of the vacuum vessel.

Abstract: A drain (7) comprises a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.