Abstract: According to an image memory address assignment system, a frame memory is divided into a plurality of blocks. Upper bits of the address of the frame memory constitute a block address, and lower bits constitute an intrablock address. The block address is supplied to an address converter. The address converter has a conversion pattern ROM. The conversion pattern ROM stores conversion patterns each converting the input write address signal block address to a block address for a completely read block area so as to perform simultaneous read and write access even if the data read direction (order) of the frame memory is different from the data write direction. The address converter supplies the write block address to the frame memory. As a result, the data can be written in the completely read block.

Abstract: In a pattern data conversion processing system, one-character pattern data generated by a character generator is divided by a shift register into a plurality of basic pattern data. The divided basic pattern data are sequentially subjected to enlargement, 90.degree. conversion or nonrotational conversion by using a 4/3 times elongation conversion ROM, a double elongation/90.degree. conversion ROM and a bypass circuit. The converted one-character data is stored in a one-character ROM and, as such, the one-character pattern data from the one-character ROM is stored by a direct memory access controller (DMAC) into a frame memory. When 180.degree. conversion is designated, the one-character data is subjected to 90.degree. conversion, and the converted data is stored in the frame memory. The pattern data from the frame memory is transferred by the DMAC to a page printer which then prints the transferred data.