Patents by Inventor Hideki Kurita
Hideki Kurita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901170Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a WARP value of 3.5 ?m or less, as measured with the back surface of the indium phosphide substrate facing upward.Type: GrantFiled: June 4, 2020Date of Patent: February 13, 2024Assignee: JX METALS CORPORATIONInventors: Shunsuke Oka, Hideki Kurita, Kenji Suzuki
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Patent number: 11894225Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a BOW value of ?2.0 to 2.0 ?m, as measured with the back surface of the indium phosphide substrate facing upward.Type: GrantFiled: June 4, 2020Date of Patent: February 6, 2024Assignee: JX METALS CORPORATIONInventors: Shunsuke Oka, Hideki Kurita, Kenji Suzuki
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Patent number: 11788203Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a SORI value of 2.5 ?m or less, as measured with the back surface of the indium phosphide substrate facing upward.Type: GrantFiled: June 4, 2020Date of Patent: October 17, 2023Assignee: JX METALS CORPORATIONInventors: Shunsuke Oka, Hideki Kurita, Kenji Suzuki
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Publication number: 20220316092Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a SORI value of 2.5 ?m or less, as measured with the back surface of the indium phosphide substrate facing upward.Type: ApplicationFiled: June 4, 2020Publication date: October 6, 2022Applicant: JX Nippon Mining & Metals CorporationInventors: Shunsuke OKA, Hideki KURITA, Kenji SUZUKI
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Publication number: 20220310381Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a WARP value of 3.5 ?m or less, as measured with the back surface of the indium phosphide substrate facing upward.Type: ApplicationFiled: June 4, 2020Publication date: September 29, 2022Applicant: JX Nippon Mining & Metals CorporationInventors: Shunsuke OKA, Hideki KURITA, Kenji SUZUKI
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Publication number: 20220310382Abstract: Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a BOW value of ?2.0 to 2.0 ?m, as measured with the back surface of the indium phosphide substrate facing upward.Type: ApplicationFiled: June 4, 2020Publication date: September 29, 2022Applicant: JX Nippon Mining & Metals CorporationInventors: Shunsuke OKA, Hideki KURITA, Kenji SUZUKI
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Publication number: 20220199770Abstract: Provided is an indium phosphide substrate having good accuracy of flatness of the orientation flat, and a method for producing the indium phosphide substrate. An indium phosphide substrate having a main surface and an orientation flat, wherein a difference between maximum and minimum values of a maximum height Pz in each of four cross-sectional curves is less than or equal to 1.50/10000 of a length in a longitudinal direction of an orientation flat end face, wherein the four cross-sectional curves are set at intervals of one-fifth of a thickness of the substrate on a surface excluding a width portion of 3 mm inward from both ends of the orientation flat end face in the longitudinal direction of the orientation flat end face, and the maximum height Pz in each of the four cross-sectional curves is measured in accordance with JIS B 0601:2013.Type: ApplicationFiled: May 26, 2021Publication date: June 23, 2022Applicant: JX NIPPON MINING & METALS CORPORATIONInventors: Kenya ITANI, Hideki KURITA, Hideaki HAYASHI
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Publication number: 20220189883Abstract: Provided is an indium phosphide substrate having good linearity accuracy of a ridge line where the main surface is in contact with the orientation flat, and a method for producing the indium phosphide substrate. An indium phosphide substrate having a main surface and an orientation flat, wherein a maximum value of deviation is less than 1/1000 of a length of a ridge line where the main surface is in contact with the orientation flat, when a plurality of measurement points are set at intervals of 2 mm from a start point to an end point at the ridge line, except for a length portion of 3 mm inward from both ends of the ridge line, and based on a reference line which is a straight line connecting the start point and the end point, a distance of each measurement point from the reference line is defined as the deviation of each measurement point.Type: ApplicationFiled: May 26, 2020Publication date: June 16, 2022Applicant: JX NIPPON MINING & METALS CORPORATIONInventors: Kenya ITANI, Hideki KURITA, Hideaki HAYASHI
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Patent number: 10679842Abstract: The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from ?1.0 ?m to 1.0 ?m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm2 or higher.Type: GrantFiled: April 6, 2018Date of Patent: June 9, 2020Assignee: JX Nippon Mining & Metals CorporationInventors: Taku Yoshida, Hideki Kurita
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Publication number: 20190189421Abstract: The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from ?1.0 ?m to 1.0 ?m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm2 or higher.Type: ApplicationFiled: April 6, 2018Publication date: June 20, 2019Applicant: JX Nippon Mining & Metals CorporationInventors: Taku YOSHIDA, Hideki KURITA
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Patent number: 8513775Abstract: Provided is a CdTe-based semiconductor substrate for epitaxial growth, which is capable of growing good-quality epitaxial crystals without urging a substrate user to implement etching treatment before the epitaxial growth. A CdTe-based semiconductor substrate, in which tracks of linear polishing damage with a depth of 1 nm or more are not observed within a viewing range of 10 ?m×10 ?m when a surface of the substrate is observed by an atomic force microscope, and orange peel defects are not observed when the surface of the substrate is visually observed under a fluorescent lamp, can grow the good-quality epitaxial crystals.Type: GrantFiled: September 30, 2010Date of Patent: August 20, 2013Assignee: JX Nippon Mining & Metals CorporationInventors: Kenji Suzuki, Hideyuki Taniguchi, Hideki Kurita, Ryuichi Hirano
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Patent number: 7875957Abstract: Provided is a semiconductor substrate for epitaxial growth which does not require any etching treatment as a pretreatment in the stage of performing an epitaxial growth of HgCdTe film. A CdTe system compound semiconductor substrate for the epitaxial growth of the HgCdTe film is housed in an inactive gas atmosphere, in a predetermined period of time (for example, 10 hours) after mirror finish treatment thereof, to thereby regulate the proportion of Te oxide of the total amount of Te on the substrate surface which is obtained by XPS measurement so as to be not more than 30%.Type: GrantFiled: August 17, 2007Date of Patent: January 25, 2011Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Kenji Suzuki, Ryuichi Hirano, Hideki Kurita
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Patent number: 7745854Abstract: It is to provide a substrate for growing a semiconductor, which is effective for suppressing an occurrence of surface defects different in type from hillock defects in case of epitaxially growing a compound semiconductor layer, particularly an Al-based compound semiconductor layer. In a substrate for growing a compound semiconductor, in which a crystal surface inclined at a predetermined off angle with respect to a (100) plane is a principal plane, an angle made by a direction of a vector obtained by projecting a normal vector of the principal plane on the (100) plane and one direction of a [0-11] direction, a [01-1] direction, a [011] direction and a [0-1-1] direction is set to be less than 35°, and the compound semiconductor layer is epitaxially grown on the substrate.Type: GrantFiled: February 2, 2007Date of Patent: June 29, 2010Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Hideki Kurita, Ryuichi Hirano
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Publication number: 20090269271Abstract: Provided is a semiconductor substrate for epitaxial growth which does not require any etching treatment as a pretreatment in the stage of performing an epitaxial growth of HgCdTe film. A CdTe system compound semiconductor substrate for the epitaxial growth of the HgCdTe film is housed in an inactive gas atmosphere, in a predetermined period of time (for example, 10 hours) after mirror finish treatment thereof, to thereby regulate the proportion of Te oxide of the total amount of Te on the substrate surface which is obtained by XPS measurement so as to be not more than 30%.Type: ApplicationFiled: August 17, 2007Publication date: October 29, 2009Inventors: Kenji Suzuki, Ryuichi Hirano, Hideki Kurita
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Patent number: 7510082Abstract: The present invention relates to a wafer storage container which contains a semiconductor wafer one by one and provides a technology to effectively reduce adhesion of particles on semiconductor wafer surfaces during the storage of the wafer. A wafer storage container which contains a wafer one by one, includes: a wafer containing member including a domed-shape recess which abuts on a circumferential edge of the wafer and is capable of holding the wafer; and a cover member which is engaged with the wafer containing member and is capable of sealing the wafer containing member; and a wafer rear surface protection member which is formed into a shape substantially same as an opening of the domed-shape recess and comes into contact with an entire rear surface of the wafer placed so that a front surface is directed the domed-shape recess.Type: GrantFiled: March 23, 2005Date of Patent: March 31, 2009Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Masayuki Kimura, Ryuichi Hirano, Hideki Kurita
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Publication number: 20090025629Abstract: It is to provide a substrate for growing a semiconductor, which is effective for suppressing an occurrence of surface defects different in type from hillock defects in case of epitaxially growing a compound semiconductor layer, particularly an Al-based compound semiconductor layer. In a substrate for growing a compound semiconductor, in which a crystal surface inclined at a predetermined off angle with respect to a (100) plane is a principal plane, an angle made by a direction of a vector obtained by projecting a normal vector of the principal plane on the (100) plane and one direction of a [0-11] direction, a [01-1] direction, a [011] direction and a [0-1-1] direction is set to be less than 35°, and the compound semiconductor layer is epitaxially grown on the substrate.Type: ApplicationFiled: February 2, 2007Publication date: January 29, 2009Inventors: Hideki Kurita, Ryuichi Hirano
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Patent number: 7338902Abstract: An epitaxial growth method includes: supporting a substrate for growth (for example, an InP substrate) with a substrate supporter, growing a compound semiconductor layer comprising 3 or 4 elements (for example, a III-V group compound semiconductor such as an InGaAs layer, AlGaAs layer, AlInAs layer and AlInGaAs layer) on the substrate for growth by metal organic chemical vapor deposition, polishing the substrate so that an angle of gradient is 0.00° to 0.03° or 0.04° to 0.24° with respect to (100) direction in the entire effective area of the substrate, and forming the compound semiconductor layer to be 0.5 ?m thick or more on the substrate by using the substrate for growth.Type: GrantFiled: May 14, 2003Date of Patent: March 4, 2008Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Masashi Nakamura, Hideki Kurita
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Publication number: 20070221519Abstract: The present invention relates to a wafer storage container which contains a semiconductor wafer one by one and provides a technology to effectively reduce adhesion of particles on semiconductor wafer surfaces during the storage of the wafer. A wafer storage container which contains a wafer one by one, includes: a wafer containing member including a domed-shape recess which abuts on a circumferential edge of the wafer and is capable of holding the wafer; and a cover member which is engaged with the wafer containing member and is capable of sealing the wafer containing member; and a wafer rear surface protection member which is formed into a shape substantially same as an opening of the domed-shape recess and comes into contact with an entire rear surface of the wafer placed so that a front surface is directed the domed-shape recess.Type: ApplicationFiled: March 23, 2005Publication date: September 27, 2007Inventors: Masayuki Kimura, Ryuichi Hirano, Hideki Kurita
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Publication number: 20060012010Abstract: An epitaxial growth method includes: supporting a substrate for growth (for example, an InP substrate) with a substrate supporter, growing a compound semiconductor layer comprising 3 or 4 elements (for example, a III-V group compound semiconductor such as an InGaAs layer, AlGaAs layer, AlInAs layer and AlInGaAs layer) on the substrate for growth by metal organic chemical vapor deposition, polishing the substrate so that an angle of gradient is 0.00° to 0.03° or 0.04° to 0.24° with respect to (100) direction in the entire effective area of the substrate, and forming the compound semiconductor layer to be 0.5 ?m thick or more on the substrate by using the substrate for growth.Type: ApplicationFiled: May 14, 2003Publication date: January 19, 2006Inventors: Masashi Nakamura, Hideki Kurita
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Patent number: 6900522Abstract: In a semiconductor wafer (W) having a periphery thereof chamfered, and having at least a main surface side thereof subjected to mirror finishing, an inclined surface (21) is formed on the periphery of the wafer, such that has an angle (?) of inclination of the inclined surface (21) with respect to a main surface (10) is not smaller than 5° and not larger than 25°, and at the same time a length (L) of the same in the radial direction of the wafer is 100 ?m or longer. Further, the inclined surface is configured to have a non-mirror-finished portion (21b) toward the periphery of the wafer.Type: GrantFiled: December 17, 2002Date of Patent: May 31, 2005Assignee: Nikko Materials Co., Ltd.Inventors: Hideki Kurita, Masashi Nakamura