Patents by Inventor Hideki Matsuhashi

Hideki Matsuhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9646961
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one TS-short-related failure mode, and one metal-short-related failure mode.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 9, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9627370
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 18, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9627371
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 18, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 7078817
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: July 18, 2006
    Assignee: Board of Regents, The University of Texas System
    Inventors: Paul S. Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Patent number: 6919639
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: July 19, 2005
    Assignee: The Board of Regents, the University of Texas System
    Inventors: Paul S. Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Publication number: 20050093163
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Application
    Filed: December 13, 2004
    Publication date: May 5, 2005
    Inventors: Paul Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Publication number: 20040070078
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Inventors: Paul S. Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Patent number: 6495461
    Abstract: A semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole, and the barrier layer provided on the bottom comprises amorphous titanium silicon nitride. This can provide a structure that has a barrier layer with a low contact resistance, enables formation of a conductor film of good quality on the barrier layer, and can attain a good electrical conduction even at fine contact holes.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: December 17, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Tsubouchi, Kazuya Masu, Hideki Matsuhashi
  • Publication number: 20020017658
    Abstract: A semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole, and the barrier layer provided on the bottom comprises amorphous titanium silicon nitride.
    Type: Application
    Filed: September 19, 2001
    Publication date: February 14, 2002
    Inventors: Kazuo Tsubouchi, Kazuya Masu, Hideki Matsuhashi
  • Publication number: 20010045660
    Abstract: A semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole, and the barrier layer provided on the bottom comprises amorphous titanium silicon nitride.
    Type: Application
    Filed: September 9, 1998
    Publication date: November 29, 2001
    Inventors: KAZUO TSUBOUCHI, KAZUYA MASU, HIDEKI MATSUHASHI