Abstract: Provided is a processing apparatus including a processing unit that is connected to a data bus, and performs control involved with an image which is output by each of a plurality of image sensors connected to the data bus, through the data bus.

Abstract: Provided is a processing apparatus including a processing unit that is connectable to a data bus, and performs output control on respective images captured by a plurality of image sensors connected to the data bus during a predetermined period of time. A timing of output of the image performed by each of the plurality of image sensors is changed by the output control.

Abstract: Provided is an image sensor that is connected to a data bus to which another image sensor is connected and image data is transmitted, and a collision detection line to which the another image sensor is connected and which is pulled up to a voltage at a first level through a register. The image sensor determines, on a basis of a state of the collision detection line, whether a collision of pieces of the image data is to occur on the data bus when the image data is output, and then outputs the image data to the data bus.

Abstract: Provided is a processing apparatus including a processing unit that is connected to a data bus, and performs control involved with an image which is output by each of a plurality of image sensors connected to the data bus, through the data bus.

Abstract: Provided is an image sensor configured to function as a synchronous master that controls synchronous imaging performed by a plurality of image sensors. In a case where a stop request is acquired, the image sensor stops imaging operation on the basis of the stop request, and does not transmit, to a different image sensor functioning as a synchronous slave that performs imaging under control by the synchronous master, a synchronous slave synchronous signal for controlling imaging timing of an image sensor functioning as the synchronous slave on the basis of the stop request.

Abstract: Provided is a processing apparatus including a processing unit that is connected to a data bus, and performs control involved with an image which is output by each of a plurality of image sensors connected to the data bus, through the data bus.

Abstract: Provided is an image sensor that is connected to a data bus to which another image sensor is connected and image data is transmitted, and a collision detection line to which the another image sensor is connected and which is pulled up to a voltage at a first level through a register. The image sensor determines, on a basis of a state of the collision detection line, whether a collision of pieces of the image data is to occur on the data bus when the image data is output, and then outputs the image data to the data bus.

Abstract: Provided is an image sensor configured to function as a synchronous master that controls synchronous imaging performed by a plurality of image sensors. In a case where a stop request is acquired, the image sensor stops imaging operation on the basis of the stop request, and does not transmit, to a different image sensor functioning as a synchronous slave that performs imaging under control by the synchronous master, a synchronous slave synchronous signal for controlling imaging timing of an image sensor functioning as the synchronous slave on the basis of the stop request.

Abstract: Provided is a processing apparatus including a processing unit that is connected to a data bus, and performs control involved with an image which is output by each of a plurality of image sensors connected to the data bus, through the data bus.

Abstract: Provided is a processing apparatus including a processing unit that is connectable to a data bus, and performs output control on respective images captured by a plurality of image sensors connected to the data bus during a predetermined period of time. A timing of output of the image performed by each of the plurality of image sensors is changed by the output control.

Abstract: A bus system includes: a first connection apparatus and a second connection apparatus carrying-out an exchange in accordance with a predetermined protocol; a bus through which the first and second connection apparatuses are connected to each other; and a bridge inserted between the first connection apparatus and the bus, and carrying out an exchange with the second connection apparatus in accordance with the predetermined protocol instead of the first connection apparatus when receiving a disconnection instruction for the first connection apparatus.

Abstract: An access key generating apparatus includes: a bit field converting unit which converts a partial bit field into a reduced bit field having a bit width shorter than a bit width of the partial bit field; an access key retaining unit which retains a plurality of access keys to control access to a memory from peripheral devices in association with each of the peripheral devices; and an indexing unit which indexes the access keys from the access key retaining unit using an index address including the reduced bit field if the conversion of the partial bit field into the reduced bit field is successful, and indexes the access keys from the access key retaining unit using an index address including the partial bit field if the conversion of the partial bit field into the reduced bit field is unsuccessful.

Abstract: Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.

Abstract: A bus system includes: a first connection apparatus and a second connection apparatus carrying-out an exchange in accordance with a predetermined protocol; a bus through which the first and second connection apparatuses are connected to each other; and a bridge inserted between the first connection apparatus and the bus, and carrying out an exchange with the second connection apparatus in accordance with the predetermined protocol instead of the first connection apparatus when receiving a disconnection instruction for the first connection apparatus.

Abstract: A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.

Abstract: There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.

Abstract: An access key generating apparatus includes: a bit field converting unit which converts a partial bit field into a reduced bit field having a bit width shorter than a bit width of the partial bit field; an access key retaining unit which retains a plurality of access keys to control access to a memory from peripheral devices in association with each of the peripheral devices; and an indexing unit which indexes the access keys from the access key retaining unit using an index address including the reduced bit field if the conversion of the partial bit field into the reduced bit field is successful, and indexes the access keys from the access key retaining unit using an index address including the partial bit field if the conversion of the partial bit field into the reduced bit field is unsuccessful.

Abstract: Introduced is an end-point bridge that relays an end point—formed by an external bus in a device tree managed by a first processor unit and an end point formed by an external bus in a device tree managed by a second processor unit. A conversion unit in the end-point bridge replaces a requestor ID contained in an access request packet, for example, which has reached the end point, to the ID of the end point from the ID of a host bridge. The ID of the host bridge is stored in a memory in a manner that the ID of the host bridge is associated with a tag of the packet, and is used to return the requestor ID when a response packet to the request reaches the end point.

Abstract: A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.

Abstract: There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.