Patents by Inventor Hideki Miyasaka

Hideki Miyasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962105
    Abstract: A coupling method of coupling a flexible flat cable to a connector by a robot, includes a preparation step of preparing the connector having an insertion hole into which the flat cable is inserted and a seat having an introduction surface placed at a front side of the insertion hole and continuously coupled to the insertion hole, a first moving step of gripping the flat cable and moving the flat cable to a position facing the seat; and a pressing step of bringing the flat cable into contact with the introduction surface in a posture inclined relative to the seat with an end of the flat cable facing the insertion hole side and pressing the flat cable against the introduction surface, and moving the end toward the connector side.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: April 16, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hideki Hata, Masaki Miyasaka
  • Patent number: 10625677
    Abstract: A display device applied to an instrument panel unit includes: a projection surface provided on a surface on a vehicle interior side of an interior member provided on the vehicle interior side of a vehicle and on a front side in a vehicle front-back direction, the interior member extending along a vehicle width direction; a projector including a projection unit configured to project an image; and a holding unit configured to hold the projector by the interior member in a positional relationship where at least a part of the projection unit is located on the projection surface side of the interior member, and the image from the projection unit is projected onto the projection surface.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 21, 2020
    Assignee: YAZAKI CORPORATION
    Inventor: Hideki Miyasaka
  • Patent number: 10369929
    Abstract: A display device and a vehicle door include a projection surface provided on a surface on a vehicle interior side of a door body provided at a vehicle, a projector configured to project an image, and a holding unit configured to hold the projector at the door body, in such a positional relationship that the image from the projector is projected on the projection surface. Thus, the display device and the vehicle door can effectively project an image appropriately on the vehicle door body.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 6, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Hideki Miyasaka
  • Publication number: 20180126908
    Abstract: A display device applied to an instrument panel unit includes: a projection surface provided on a surface on a vehicle interior side of an interior member provided on the vehicle interior side of a vehicle and on a front side in a vehicle front-back direction, the interior member extending along a vehicle width direction; a projector including a projection unit configured to project an image; and a holding unit configured to hold the projector by the interior member in a positional relationship where at least a part of the projection unit is located on the projection surface side of the interior member, and the image from the projection unit is projected onto the projection surface.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 10, 2018
    Applicant: Yazaki Corporation
    Inventor: Hideki MIYASAKA
  • Publication number: 20180079362
    Abstract: A display device and a vehicle door include a projection surface provided on a surface on a vehicle interior side of a door body provided at a vehicle, a projector configured to project an image, and a holding unit configured to hold the projector at the door body, in such a positional relationship that the image from the projector is projected on the projection surface. Thus, the display device and the vehicle door can effectively project an image appropriately on the vehicle door body.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 22, 2018
    Applicant: Yazaki Corporation
    Inventor: Hideki MIYASAKA
  • Publication number: 20170282799
    Abstract: A driving support device includes a projector and a screen in a cabin. The projector projects an image based on driving support information serving as assistance at the time of driving a vehicle. The screen includes a projection part on which the image based on the driving support information projected from a projecting unit of the projector is projected. The projecting unit of the projector and the projection part of the screen are disposed in a lower side of the vehicle with respect to an eye point of a driver, and the projecting unit of the projector is disposed in a lower side of the vehicle with respect to the gravity center position of the projection part of the screen. The projector is disposed so that reflection light related to an image based on the driving support information incident from the projecting unit reaches the eye point of the driver.
    Type: Application
    Filed: March 27, 2017
    Publication date: October 5, 2017
    Applicant: Yazaki Corporation
    Inventor: Hideki MIYASAKA
  • Publication number: 20040184528
    Abstract: In a data processing system in which a plurality of data processing apparatuses are connected together via a communication network, each of the plurality of data processing apparatuses includes a data acquisition part obtaining data which should be processed; a data analysis part performing predetermined data analysis on the obtained data; a data unit identification part identifying the obtained data as a data unit for each event; and a determining unit determining for each data unit according to a predetermined condition whether the predetermined data analysis is performed on the obtained data should be processed in the own apparatus, or is sent to another apparatus and is performed on by the anointer apparatus the predetermined data analysis.
    Type: Application
    Filed: January 26, 2004
    Publication date: September 23, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Hideki Miyasaka, Kaname Yoshida, Yasuo Misuda
  • Patent number: 6661594
    Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Satoh, Seiichi Mita, Shoichi Miyazawa, Terumi Takashi, Yosuke Hori, Yoshiju Watanabe, Akihiko Hirano, Satoshi Minoshima, Hideki Miyasaka, Toshihiro Nitta, Tomoaki Hirai, Ryushi Shimokawa, Koji Shida, Yasuhide Ouchi
  • Publication number: 20030035236
    Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.
    Type: Application
    Filed: October 23, 2002
    Publication date: February 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Naoki Satoh, Seiichi Mita, Shoichi Miyazawa, Terumi Takashi, Yosuke Hori, Yoshiju Watanabe, Akihiko Hirano, Satoshi Minoshima, Hideki Miyasaka, Toshihiro Nitta, Tomoaki Hirai, Ryushi Shimokawa, Koji Shida, Yasuhide Ouchi
  • Patent number: 6490003
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: December 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Patent number: 6490004
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: December 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Patent number: 6483549
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: November 19, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20020057376
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 16, 2002
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20020057377
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 16, 2002
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20020057375
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 16, 2002
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Patent number: 6317163
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: November 13, 2001
    Assignee: Fujitsu Ltd.
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20010009483
    Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.
    Type: Application
    Filed: February 20, 2001
    Publication date: July 26, 2001
    Inventors: Naoki Satoh, Seiichi Mita, Shoichi Miyazawa, Terumi Takashi, Yosuke Hori, Yoshiju Watanabe, Akihiko Hirano, Satoshi Minoshima, Hideki Miyasaka, Toshihiro Nitta, Tomoaki Hirai, Ryushi Shimokawa, Koji Shida, Yasuhide Ouchi
  • Patent number: 5991503
    Abstract: An encoding unit encodes and compresses picture data in a bit map format corresponding to the MPEG method. A packet assembling portion assembles the picture data encoded by the encoding unit as packets in the format corresponding to the MPEG method, and stores the packets to a storing medium. At this point, the packet assembling portion writes an I picture index to a packet that contains at least a part of I picture data. When a special reproducing operation is performed, a data storing unit reads only packets that have the I picture index. A decoding unit decodes only I picture data of picture data contained in packets read from the storing medium and displays the decoded picture data.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: November 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hideaki Watanabe, Takehira Masanori, Kiyoshi Maeda, Masao Mutou, Hirohiko Inagaki
  • Patent number: 5841303
    Abstract: Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: November 24, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Terumi Takashi, Kazunori Iwabuchi, Minoru Kosuge, Hiromi Matsushige, Hideki Miyasaka
  • Patent number: 5818655
    Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: October 6, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Satoh, Seiichi Mita, Shoichi Miyazawa, Terumi Takashi, Yosuke Hori, Yoshiju Watanabe, Akihiko Hirano, Satoshi Minoshima, Hideki Miyasaka, Toshihiro Nitta, Tomoaki Hirai, Ryushi Shimokawa, Koji Shida, Yasuhide Ouchi