Abstract: An audio amplifier circuit for driving an electro-acoustic transducer, which is bridged transless (BTL)-connected to the audio amplifier circuit, in a filterless manner, including: a class D amplifier including a high side transistor and a low side transistor; a high side driver configured to drive the high side transistor; and a low side driver configured to drive the low side transistor, as a pair, wherein the low side driver is configured so that a time for turning off the low side transistor by the low side driver is longer than that for turning off the high side transistor by the high side driver.

Abstract: An audio amplifier circuit for driving an electro-acoustic transducer, which is bridged transless (BTL)-connected to the audio amplifier circuit, in a filterless manner, including: a class D amplifier including a high side transistor and a low side transistor; a high side driver configured to drive the high side transistor; and a low side driver configured to drive the low side transistor, as a pair, wherein the low side driver is configured so that a time for turning off the low side transistor by the low side driver is longer than that for turning off the high side transistor by the high side driver.

Abstract: An audio output circuit for driving an electro-acoustic transducer includes first and second D-class amplifiers, a pulse modulator to receive an audio signal and generate first and second pulse signals for driving first and second D-class amplifiers, first and second drivers to drive first and second D-class amplifiers in response to first and second pulse signals, respectively, a common mode choke coil, and a delay setting circuit to apply a relative delay to output signals of the first and second D-class amplifiers.

Abstract: An audio output circuit for driving an electro-acoustic transducer includes first and second D-class amplifiers, a pulse modulator to receive an audio signal and generate first and second pulse signals for driving first and second D-class amplifiers, first and second drivers to drive first and second D-class amplifiers in response to first and second pulse signals, respectively, a common mode choke coil, and a delay setting circuit to apply a relative delay to output signals of the first and second D-class amplifiers

Abstract: In an audio signal amplifying circuit, a main amplifier and a sub amplifier amplify an audio signal. The sub amplifier is disposed in parallel with the main amplifier and also is set to have a lower driving capability than the main amplifier. A control unit controls the on and off of the main amplifier. The control unit turns the main amplifier off when it is determined that the audio signal is in a mute state. An audio signal amplified by the main amplifier and the sub amplifier passes through a low-pass filter to be converted into an analog signal and is output to a speaker.

Abstract: A selection circuit switches the output between a ancillary PWM signal NSPWM and a primary PWM signal SPWM in accordance with a power supply transition period or normal period. A ancillary signal generating circuit generates a gradually rising signal which is then amplified by a second driver circuit, so that a DC block capacitor is gradually charged and discharged. Thereby, the occurrence of noise due to an inrush current is prevented.