Patents by Inventor Hideki Murase

Hideki Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer printed circuit board, method of producing multilayer printed circuit board and resin filler
    Patent number: 6251502
    Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor insulating circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: June 26, 2001
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshihiko Yasue, Yasuji Hiramatsu, Hideki Yano, Yoshifumi Ishitani, Yoichiro Kawamura, Hideki Murase, Ayumi Suzuki, Masato Kawade, Motoo Asai
  • Multilayer printed circuit board, method of producing multilayer printed circuit board and resin filler
    Patent number: 6217988
    Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor insulating circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: April 17, 2001
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshihiko Yasue, Yasuji Hiramatsu, Hideki Yano, Yoshifumi Ishitani, Yoichiro Kawamura, Hideki Murase, Ayumi Suzuki, Masato Kawade, Motoo Asai
  • Multilayer printed circuit board, method of producing multilayer printed circuit board and resin filler
    Patent number: 6010768
    Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor insulating circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: January 4, 2000
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshihiko Yasue, Yasuji Hiramatsu, Hideki Yano, Yoshifumi Ishitani, Yoichiro Kawamura, Hideki Murase, Ayumi Suzuki, Masato Kawade, Motoo Asai