Patents by Inventor Hideki Murayama
Hideki Murayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12131024Abstract: A memory system including: a nonvolatile memory; first and second decoders configured to execute first and second error correction for correcting data read from the nonvolatile memory; and a controller configured to receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command, and after receiving the first command, output data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.Type: GrantFiled: June 1, 2023Date of Patent: October 29, 2024Assignee: Kioxia CorporationInventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
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Patent number: 7080227Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: GrantFiled: February 5, 2002Date of Patent: July 18, 2006Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
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Patent number: 7062627Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: GrantFiled: August 19, 2003Date of Patent: June 13, 2006Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
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Patent number: 6970912Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.Type: GrantFiled: May 18, 1999Date of Patent: November 29, 2005Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Hiroshi Yashiro, Satoshi Yoshizawa, Kazuo Horikawa, Takehisa Hayashi, Hiroshi Iwamoto, Kimitoshi Yamada
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Publication number: 20040054865Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: ApplicationFiled: August 19, 2003Publication date: March 18, 2004Applicant: Hitachi, LimitedInventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
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Patent number: 6684312Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: GrantFiled: January 8, 1999Date of Patent: January 27, 2004Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
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Publication number: 20030126420Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.Type: ApplicationFiled: May 18, 1999Publication date: July 3, 2003Inventors: HIDEKI MURAYAMA, HIROSHI YASHIRO, SATOSHI YOSHIZAWA, KAZUO HORIKAWA, TAKEHISA HAYASHI, HIROSHI IWAMOTO, KIMITOSHI YAMADA
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Patent number: 6557034Abstract: Before transferring data, a transmitting computer acquires a transfer rate of an I/O bus to which a communication control device in a receiving computer is connected. When transmitting data, the communication control device refers to a connection control table and a receiver control table, and chooses a transmitting queue for data transmission from a plurality of transmitting queues so that an interval is inserted between transmissions of data, and the data can be transmitted to the receiving computer without loss. The transmission intervals of data are determined based on the transfer rate of the I/O bus to which the communication control device in the receiving computer is connected.Type: GrantFiled: February 3, 2000Date of Patent: April 29, 2003Assignee: Hitachi, Ltd.Inventors: Hirofumi Fujita, Hideki Murayama, Hiroshi Yashiro
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Patent number: 6477560Abstract: A control method of controlling a computer for controlling a resource connected to the computer and shared by a plurality of programs included in the computer includes the steps of storing a control information ID indicating a storage area in the main memory storing control information concerning access between a certain program and the resource in an OS space of a main memory, storing the control information ID in an adaptor connected to the main memory via a bus, and taking out the control information from the storage area included in the OS space, by using the control information ID stored in the adapter. In the case where the adapter runs short of a storage area, information that the adapter runs short of a storage area in the main memory is conveyed via the bus. By using the control information thus taken out, the resource is controlled.Type: GrantFiled: November 16, 1998Date of Patent: November 5, 2002Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Hiroshi Yashiro, Takehisa Hayashi, Masahiro Kitano
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Publication number: 20020073292Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: ApplicationFiled: February 5, 2002Publication date: June 13, 2002Applicant: Hitachi, LimitedInventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
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Publication number: 20020029325Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: ApplicationFiled: January 8, 1999Publication date: March 7, 2002Inventors: HIDEKI MURAYAMA, KAZUO HORIKAWA, HIROSHI YASHIRO, MASAHIKO YAMAUCHI, YASUHIRO ISHII, DAISUKE SASAKI
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Patent number: 6108694Abstract: A memory disc sharing method in which a plurality of computers share a memory disc through a network, wherein a command in accordance with which the memory disc is accessed is received by a network interface apparatus, and when a requested computer to which a request of the command has been made is any of other computers, the command is transmitted to the any of other computers, and when the requested computer is a computer concerned, the command is stored in a memory disc command queue. The network interface apparatus retrieves the command from the memory disc command queue, and executes the processing of reading out/writing data from/to the memory disc in the computer concerned when a requesting computer from which a request of the command has been made is the computer concerned, and carries out the data transfer between the memory disc in the computer concerned and the requesting computer when the requesting computer is any of other computers.Type: GrantFiled: November 18, 1998Date of Patent: August 22, 2000Assignee: Hitachi, Ltd.Inventors: Hiroshi Yashiro, Hideki Murayama, Hirofumi Fujita, Takehisa Hayashi, Masahiro Kitano
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Patent number: 6049221Abstract: A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs.Type: GrantFiled: July 8, 1998Date of Patent: April 11, 2000Assignee: Hitachi, Ltd.Inventors: Kenichi Ishibashi, Takehisa Hayashi, Tsutomu Goto, Hideki Murayama, Akira Yamagiwa, Yasuhiro Ishii, Naoki Hamanaka, Masabumi Shibata
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Patent number: 5935205Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.Type: GrantFiled: June 21, 1996Date of Patent: August 10, 1999Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Hiroshi Yashiro, Satoshi Yoshizawa, Kazuo Horikawa, Takehisa Hayashi, Hiroshi Iwamoto, Kimitoshi Yamada
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Patent number: 5936955Abstract: A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently receiType: GrantFiled: November 5, 1997Date of Patent: August 10, 1999Assignee: Hitachi, Ltd.Inventors: Takeshi Aimoto, Hidenori Inouchi, Shoichi Murase, Shinichi Tanabe, Kazuhiro Hashimoto, Hiroshi Iwamoto, Hiroshi Ohguro, Takehisa Hayashi, Haruyuki Nakayama, Kenji Nakajima, Satoshi Yoshizawa, Hideki Murayama
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Patent number: 5835492Abstract: A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance withType: GrantFiled: September 18, 1995Date of Patent: November 10, 1998Assignee: Hitachi, Ltd.Inventors: Takeshi Aimoto, Hidenori Inouchi, Shoichi Murase, Shinichi Tanabe, Kazuhiro Hashimoto, Hiroshi Iwamoto, Hiroshi Ohguro, Takehisa Hayashi, Haruyuki Nakayama, Kenji Nakajima, Satoshi Yoshizawa, Hideki Murayama
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Patent number: 5830577Abstract: The lubricant layer according to the present invention is used in a thin film magnetic recording medium in which a solid surface sliding at a high speed is required to retain its lubricating performance and abrasion resistance for a long period of time, comprising a host-guest complex composed of a lubricant molecule as a guest molecule and a multidentate ligand as a host compound to form the complex with the guest molecule.Type: GrantFiled: June 27, 1996Date of Patent: November 3, 1998Assignee: Mitsubishi Chemical CorporationInventors: Hideki Murayama, Keiichiro Sano, Kazuhiko Sawada, Fumiaki Yokoyama, Haruhiko Ikeuchi, Yutaka Teranishi
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Patent number: 5678062Abstract: A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing.Type: GrantFiled: February 22, 1994Date of Patent: October 14, 1997Assignee: Hitachi, Ltd.Inventors: Tetsuhiko Okada, Hideki Murayama, Takehisa Hayashi, Atsushi Ugajin, Yasuhiro Ishii, Masahiro Kitano
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Patent number: 5649102Abstract: A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer.Type: GrantFiled: November 25, 1994Date of Patent: July 15, 1997Assignee: Hitachi, Ltd.Inventors: Masahiko Yamauchi, Satoshi Yoshizawa, Hideki Murayama, Takehisa Hayashi, Akira Kito, Hiroshi Yashiro, Tsutomu Goto, Kimitoshi Yamada, Toru Horimoto
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Patent number: 5617424Abstract: The present invention relates to a network communication method and a network system that enables received data to be transferred directly to the user data region, thereby eliminating the need to perform data copy operations. In the present invention, packets are each provided with received region assignment information (port ID) for showing the region in which the packet is to be received and/or division information for dividing the packet. The region which is to receive data contained in the packet is determined from a port table and conversion tables, and the packet data is transferred to the region directly.Type: GrantFiled: May 3, 1996Date of Patent: April 1, 1997Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Satoshi Yoshizawa, Hidenori Inouchi, Takeshi Aimoto, Takehisa Hayashi, Hiroshi Iwamoto