Abstract: A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer.

Abstract: A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.

Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising: a first sacrificial oxidation stage for removing material constituting the working layer (6) over a certain surface thickness of each substrate (1), a stage of polishing (200) the face which has been subjected to the first sacrificial oxidation stage (100), and a second sacrificial oxidation stage for again removing material constituting the working layer (6) on the polished face (17).

Abstract: A semiconductor substrate that prevents formation of particles from an edge part of the substrate. The substrate contains an on-substrate oxide film and an SOI layer stacked on the oxide film. A molten layer is formed on the edge part of the on-substrate oxide film and the SOI layer by mixing the SOI layer and the on-substrate oxide film to cover the edge part. An epitaxial layer may also be formed on the edge part of the on-substrate oxide film and the SOI layer to cover the edge part.

Abstract: A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).

Abstract: It is an object to obtain a method of inspecting a semiconductor wafer which can carry out an inspection accurately. At a step S11, a virtual divided wafer is generated based on dividing cell size data and dividing cell arrangement data which define a dividing condition. At a step S12, an inspection result information database is checked over the virtual divided wafer to calculate a nonstandard cell number (C0) having a nonstandard portion and a standard cell number (C1) having no nonstandard portion, respectively. At a step S13, a usable area rate PUA (%) (=(C1/C10)* 100) is calculated based on a total virtual dividing unit cell number (C10) and the standard cell number (C1).

Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising:

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

Abstract: In order to obtain a method of evaluating a crystal defect which allows crystal defects generated in a thin film SOI layer or a thin film surface layer to be evaluated using an in-line test, an SOI layer 3 has silicide regions 8 formed in the evaluation region consequently upon generation of crystal defects generated in the SOI layer 3. The silicide regions 8 are regions silicided as a result of the crystal defects having gettered metals which are contained in a transition layer 10 and diffuse into the SOI layer 3 upon a heat treatment. A laser beam is irradiated to the evaluation region via the transition layer 10 and the silicon oxide film 6. By monitoring a current flowing between first and second probes using an ampere meter while scanning the evaluation region with a laser beam, it is possible to evaluate the crystal defects in the evaluation region.

Abstract: A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

Abstract: An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

Abstract: In order to obtain a method of evaluating a crystal defect which allows crystal defects generated in a thin film SOI layer or a thin film surface layer to be evaluated using an in-line test, an SOI layer 3 has silicide regions 8 formed in the evaluation region consequently upon generation of crystal defects generated in the SOI layer 3. The silicide regions 8 are regions silicided as a result of the crystal defects having gettered metals which are contained in a transition layer 10 and diffuse into the SOI layer 3 upon a heat treatment. A laser beam is irradiated to the evaluation region via the transition layer 10 and the silicon oxide film 6. By monitoring a current flowing between first and second probes using an ampere meter while scanning the evaluation region with a laser beam, it is possible to evaluate the crystal defects in the evaluation region.

Abstract: An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

Abstract: A manufacturing method of a SOI substrate (10) comprises the steps of: forming an oxide film (12) at cross-sectional both main surfaces and cross-sectional both end surfaces of a silicon substrate (11); forming a resist layer (13) on the oxide film (12) at cross-sectional both end surfaces of the substrate (11); and removing the oxide film (12) at those portions which are left from the covering of the resist layer (13), to thereby expose the both main surfaces of the substrate (11). Next, the resist layer (13) is removed to thereby leave the oxide film (12) at the both end surfaces of the substrate (11); and oxygen ions (I) are dosed into the substrate (11) from one of the exposed both main surfaces, followed by an anneal processing to thereby form an oxide layer (14) in a region at a predetermined depth from the one main surface of the substrate (11). The oxide film (12) left on the both end surfaces of the substrate (11) is then removed.

Abstract: A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.