Patents by Inventor Hideki Oku

Hideki Oku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230311300
    Abstract: A servo motor includes: a driving section including a rotor and stator; an input shaft configured such that a driving force of the driving section is transferred to the input shaft, wherein the input shaft is configured to be integral and rotated with the rotor; a reduction gear configured to output the driving force from the input shaft by reducing a rotational speed of the input shaft; an output shaft configured such that the driving force which has been transferred to the input shaft is transferred to the output shaft via the reduction gear; an input encoder disc attached to the input shaft; an output encoder disc attached to the output shaft; a circuit board including a predetermined circuit pattern; an input sensor mounted on the circuit board, wherein the input sensor is oriented toward the input encoder disc; and an output sensor mounted on the circuit board, wherein the output sensor is oriented toward the output encoder disc; wherein at least one of the input sensor or the output sensor is mounted on
    Type: Application
    Filed: September 21, 2021
    Publication date: October 5, 2023
    Inventors: Shotaro KUDO, Toru KONO, Ryosei KURAMOTO, Hidetoshi MURAMATSU, Tomohiro KOMIYAMA, Yuri MIYAMA, Hideki OKU
  • Publication number: 20200161830
    Abstract: A driver for outputting a drive signal to drive a direct-modulation semiconductor laser includes a compensation signal generator configured to produce a compensation signal that increases a drive current value at an end of a delay period following a positive transition of an “on” period of the drive signal during which an “on” state continues.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 21, 2020
    Inventor: Hideki Oku
  • Publication number: 20190312558
    Abstract: An amplifier circuit includes a first amplifier including input terminals and configured to amplify a signal, the signal being input into one of the input terminals; a second amplifier into which positive and negative outputs of the first amplifier are each input; a first low-pass filter into which outputs of the second amplifier are input; a high-pass filter into which outputs of the first amplifier are input; a second low-pass filter into which outputs of the high-pass filter are input; and a difference circuit configured to output a difference between outputs of the first low-pass filter and outputs of the second low-pass filter, wherein an output of the difference circuit is input into another one of the input terminals of the first amplifier.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 10, 2019
    Inventor: Hideki Oku
  • Patent number: 10263567
    Abstract: An amplifier circuit includes a first transistor; a first resistor to which a first potential is applied, the first resistor being connected to an emitter of the first transistor; a second resistor to which a second potential is applied, the second resistor being connected to a collector of the first transistor; and a signal control circuit configured to apply, to a base of the first transistor, a voltage that has been level-shifted based on an average value of a voltage at the collector of the first transistor, the signal control circuit being provided between the collector and the base of the first transistor.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: April 16, 2019
    Assignee: FUJITSU COMPONENT LIMITED
    Inventor: Hideki Oku
  • Patent number: 10171051
    Abstract: An amplification circuit coupled to another circuit by alternating current (AC) coupling includes: an amplifier that amplifies and outputs a signal input from the other circuit or amplifies an input signal and outputs the amplified input signal to the other circuit; a feedback circuit that positively feeds back the signal output from the amplifier to an input of the amplifier; and a low pass filter that attenuates a high frequency component of the signal positively fed back to the input of the amplifier by the feedback circuit, and in which a higher cut-off frequency is set such that a lower cut-off frequency in a combination of the amplification circuit and a high pass filter formed by the AC coupling is lower than a lower cut-off frequency in the high pass filter.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 1, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Oku
  • Publication number: 20180241353
    Abstract: An amplifier circuit includes a first transistor; a first resistor to which a first potential is applied, the first resistor being connected to an emitter of the first transistor; a second resistor to which a second potential is applied, the second resistor being connected to a collector of the first transistor; and a signal control circuit configured to apply, to a base of the first transistor, a voltage that has been level-shifted based on an average value of a voltage at the collector of the first transistor, the signal control circuit being provided between the collector and the base of the first transistor.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 23, 2018
    Inventor: Hideki Oku
  • Patent number: 9755589
    Abstract: An amplifier circuit includes: a first transistor and a second transistor of which collectors/drains are coupled to a first power-source via a first load-impedance-element and the first power-source via a second load-impedance-element, respectively; a gain-adjustment-resistance-element that is connected to an emitter/source of the first transistor and an emitter/source of the second transistor; a first current-source and a second current-source that are connected to the emitters/the sources of the first transistor and the second transistor respectively, and a second power-source; a third transistor and a fourth transistor of which collectors/drains are connected to the first power-source and bases/gates are connected to the first load-impedance-element and the second load-impedance-element, respectively; a first feedback-resistance-element that is connected to a base/gate of the first transistor and an emitter/source of the third transistor; and a second feedback-resistance-element that is connected to a base
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: September 5, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Oku
  • Publication number: 20170187341
    Abstract: An amplification circuit coupled to another circuit by alternating current (AC) coupling includes: an amplifier that amplifies and outputs a signal input from the other circuit or amplifies an input signal and outputs the amplified input signal to the other circuit; a feedback circuit that positively feeds back the signal output from the amplifier to an input of the amplifier; and a low pass filter that attenuates a high frequency component of the signal positively fed back to the input of the amplifier by the feedback circuit, and in which a higher cut-off frequency is set such that a lower cut-off frequency in a combination of the amplification circuit and a high pass filter formed by the AC coupling is lower than a lower cut-off frequency in the high pass filter.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 29, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hideki Oku
  • Patent number: 9525386
    Abstract: A receiver circuit includes a first amplifier circuit to differentially amplify differential input signals by a linear operation, a second amplifier circuit configured to differentially amplify output differential signals of the first amplifier circuit by a limiting operation, a feedback circuit, first and second resistors coupled between the feedback circuit and outputs of the first amplifier circuit, and third and fourth resistors coupled between the feedback circuit and outputs of the second amplifier circuit. The feedback circuit amplifies a positive-phase signal that is output from a positive-phase output node thereof coupled to the first and third resistors, and a negative-phase signal that is output from a negative-phase output node thereof coupled to the second and fourth resistors, and feeds back a feedback signal after amplification to the first amplifier circuit.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: December 20, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Ide, Hideki Oku
  • Patent number: 9509259
    Abstract: An amplifier 12 including a first transistor 23 which is a common base transistor and whose emitter current fluctuates in accordance with fluctuations in an input current that is input to the emitter, a second transistor 24 which is a common base transistor, whose emitter is connected to the collector of the first transistor 23, and whose collector voltage fluctuates in accordance with fluctuations in the emitter current of the first transistor 23, a third transistor 31 which is a common collector transistor and whose base is connected to the collector of the second transistor 24, and an amplification unit 40 to which an emitter voltage of the third transistor 3 is input and which outputs an amplified voltage obtained by amplifying the emitter voltage of the third transistor, wherein the base resistance of the second transistor 24 is higher than the base resistance of the first transistor 23.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Oku
  • Publication number: 20160197585
    Abstract: An amplifier 12 including a first transistor 23 which is a common base transistor and whose emitter current fluctuates in accordance with fluctuations in an input current that is input to the emitter, a second transistor 24 which is a common base transistor, whose emitter is connected to the collector of the first transistor 23, and whose collector voltage fluctuates in accordance with fluctuations in the emitter current of the first transistor 23, a third transistor 31 which is a common collector transistor and whose base is connected to the collector of the second transistor 24, and an amplification unit 40 to which an emitter voltage of the third transistor 3 is input and which outputs an amplified voltage obtained by amplifying the emitter voltage of the third transistor, wherein the base resistance of the second transistor 24 is higher than the base resistance of the first transistor 23.
    Type: Application
    Filed: December 15, 2015
    Publication date: July 7, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Hideki Oku
  • Patent number: 9276733
    Abstract: A signal reproduction circuit, includes: a clock reproduction circuit configured to reproduce a reception clock from a reception data signal; a data fetching circuit configured to fetch the reception data signal in response to a variation edge of the reception clock and output the reception data signal as first decision data; and a phase adjustment circuit configured to adjust a phase of the variation edge of the reception clock in response to a plurality of second decision data, the data fetching circuit fetching a plurality of second reception data in a plurality of periods immediately preceding to a period in which the reception data signal is fetched and outputting the plurality of second reception data as the plurality of second decision data.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 1, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Oku
  • Publication number: 20150311871
    Abstract: A receiver circuit includes a first amplifier circuit to differentially amplify differential input signals by a linear operation, a second amplifier circuit configured to differentially amplify output differential signals of the first amplifier circuit by a limiting operation, a feedback circuit, first and second resistors coupled between the feedback circuit and outputs of the first amplifier circuit, and third and fourth resistors coupled between the feedback circuit and outputs of the second amplifier circuit. The feedback circuit amplifies a positive-phase signal that is output from a positive-phase output node thereof coupled to the first and third resistors, and a negative-phase signal that is output from a negative-phase output node thereof coupled to the second and fourth resistors, and feeds back a feedback signal after amplification to the first amplifier circuit.
    Type: Application
    Filed: March 24, 2015
    Publication date: October 29, 2015
    Inventors: Satoshi Ide, Hideki Oku
  • Patent number: 8890621
    Abstract: An amplifier circuit includes: an input pad to receive a current signal; a conversion section to convert the current signal into a voltage signal; an inductor electrically connected in series between the input pad and the conversion section; and a storage element, one end of the storage element electrically coupled between the inductor and the conversion section, the other end of the storage element electrically coupled to a ground.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Limited
    Inventor: Hideki Oku
  • Patent number: 8791652
    Abstract: A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Hideki Oku, Yukito Tsunoda
  • Publication number: 20140158866
    Abstract: An amplifier circuit includes: a first transistor and a second transistor of which collectors/drains are coupled to a first power-source via a first load-impedance-element and the first power-source via a second load-impedance-element, respectively; a gain-adjustment-resistance-element that is connected to an emitter/source of the first transistor and an emitter/source of the second transistor; a first current-source and a second current-source that are connected to the emitters/the sources of the first transistor and the second transistor respectively, and a second power-source; a third transistor and a fourth transistor of which collectors/drains are connected to the first power-source and bases/gates are connected to the first load-impedance-element and the second load-impedance-element, respectively; a first feedback-resistance-element that is connected to a base/gate of the first transistor and an emitter/source of the third transistor; and a second feedback-resistance-element that is connected to a base
    Type: Application
    Filed: October 7, 2013
    Publication date: June 12, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Hideki OKU
  • Patent number: 8723709
    Abstract: There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Limited
    Inventor: Hideki Oku
  • Patent number: 8655188
    Abstract: A driver circuit includes a plurality of delay circuits and an inverter. The plurality of delay circuits delay branched driving signals. The inverter inverts at least one of the branched driving signals. At least one of the plurality of delay circuits is at least one variable delay circuit delaying a variable amount of delay. The output driving signal is output by combining the inverted signal of the branched driving signal output via at least one inverter and at least one non-inverted signal of the branched driving signals output from the delay circuits.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Hideki Oku, Yukito Tsunoda
  • Patent number: 8492997
    Abstract: A driving circuit includes a first delay circuit, a rise-detection circuit, a fall-detection circuit, a first filter, a second filter, and an adder. The first delay circuit delays an input signal. The rise-detection circuit detects a rise of the input signal. The fall-detection circuit detects a fall of the input signal. The first filter gives a first gain-frequency response to an output signal of the rise-detection circuit. The second filter gives a second gain-frequency response to an output signal of the fall-detection circuit. The adder adds an output signal of the first filter and an output signal of the second filter to an output signal of the first delay circuit.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 23, 2013
    Assignee: Fujitsu Limited
    Inventor: Hideki Oku
  • Publication number: 20130120059
    Abstract: An amplifier circuit includes: an input pad to receive a current signal; a conversion section to convert the current signal into a voltage signal; an inductor electrically connected in series between the input pad and the conversion section; and a storage element, one end of the storage element electrically coupled between the inductor and the conversion section, the other end of the storage element electrically coupled to a ground.
    Type: Application
    Filed: September 5, 2012
    Publication date: May 16, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Hideki OKU