Abstract: A data processor and associated method for taking and returning from traps speculatively. The data processor supports a predefined number of trap levels for taking nested traps each having a corresponding trap level. The data processor comprises means to form checkpoints, means to back up to the checkpoints, means to take a trap, means to return from a trap, registers, and a trap stack unit. The registers have contents that define the state of the data processor each time a trap is taken. The trap stack unit includes a trap stack data storage structure that has a greater number of trap slack storage entries than there are trap levels. It also includes a freelist unit that maintains a current availability list of the trap stack storage entries that are currently available for mapping to one of the trap levels. The freelist unit identifies, each time a trap is taken, a next one of the currently available trap stack storage entries for mapping to the corresponding one of the trap levels.

Abstract: Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size.

Abstract: A cache system having a plurality of read-in ports through which data fetched from a main memory system can be transferred regardless of the type of the data fetch request. Further, each data fetch request is output from an available read-in port, during the data fetch operation for a previous data fetch request of the same type.

Abstract: A buffer memory control system for executing an immediate instruction, including a block fetch control unit for generating a first move-in complete signal indicating that the move-in of the heading subblock from a main memory to the buffer memory is completed. In response to the first move-in complete signal, the fetch and store operation starts without waiting for the completion of the move-in of a full block.