Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

Abstract: A massage unit of a massage device moves upward and downward along a backrest of a chair. A pair of therapeutic arms are pivotably supported on a pair of pivot arms projecting forward when viewed from the backrest. Therapeutic fingers on the therapeutic arms have massage balls disposed on them. The pivot arms are driven to move the therapeutic arms in three dimensions, i.e., up and down, left and right, forward and back, so that a patient is massaged by the massage balls. An angle detector detects the angle of the therapeutic arms relative to the pivot arms. The magnitude and change in the output of the detector is used to determine the portion of the patient's body that is being contacted by the massage balls at any time.

Abstract: A massage unit of a massage device moves upward and downward along a backrest of a chair. A pair of therapeutic arms are pivotably supported on a pair of pivot arms projecting forward when viewed from the backrest. Therapeutic fingers on the therapeutic arms have massage balls disposed on them. The pivot arms are driven to move the therapeutic arms in three dimensions, i.e., up and down, left and right, forward and back, so that a patient is massaged by the massage balls. An angle detecting means detects the angle of the therapeutic arms relative to the pivot arms. The magnitude and change in the output of the detecting means is used to determine the portion of the patient's body that is being contacted by the massage balls at any time.

Abstract: A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction.

Abstract: A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register.