Abstract: The present disclosure relates to a solid-state image-capturing element and electronic device capable of improving the linearity of illuminance values. The dynamic-range expander 118 expands dynamic range of a pixel value for each pixel based on the pixel value having different exposure times of a plurality of pixels. The integrator 119 integrates pixel values having the dynamic range expanded by the dynamic-range expander 118 and generates an illuminance value. The present disclosure is applicable to complementary metal-oxide semiconductor (CMOS) image sensor or the like used in, for example, an illuminometer.

Abstract: The present technique relates to an imaging device and an imaging method, an electronic device, and a program, which are configured to improve an SN ratio by combining addition reading and thin-out reading by signal processing similar to signal processing using thin-out reading. First, as illustrated in the left side of the drawing, G pixel and B pixel, which are sub-colors, of the top row of regions Z1, Z2 are subjected to thin-out reading. Next, for W pixels of the main color arranged in a checkerboard pattern in the regions Z1, Z2, two pixels tied by a straight line in the drawing are subjected to addition reading at the same tone timing. For W pixels of the main color arranged in a checkerboard pattern in regions Z3, Z4, two pixels tied by a straight line in the drawing are also subjected to addition reading at the same tone timing. R and G pixels, which are sub-colors, of the lower stage of the regions Z3, Z4 are read.

Abstract: The present disclosure relates to a solid-state image-capturing element and electronic device capable of improving the linearity of illuminance values. The dynamic-range expander 118 expands dynamic range of a pixel value for each pixel based on the pixel value having different exposure times of a plurality of pixels. The integrator 119 integrates pixel values having the dynamic range expanded by the dynamic-range expander 118 and generates an illuminance value. The present disclosure is applicable to complementary metal-oxide semiconductor (CMOS) image sensor or the like used in, for example, an illuminometer.

Abstract: There is provided a signal processing device including a correction processing unit that acquires a pixel signal output from a sensor on which pixels are disposed in an array in which a spatial frequency of a color pixel which is a pixel acquiring a color component is lower than a spatial frequency of luminance pixels which are pixels acquiring luminance components, and then corrects the pixel signal output from a defective pixel out of the pixels that the sensor includes. During correction of a pixel signal of the color pixel, the correction processing unit performs correction referring to pixel signals of the luminance pixels having a spatial frequency higher than the spatial frequency of the color pixel.

Abstract: The present technique relates to an imaging device and an imaging method, an electronic device, and a program, which are configured to improve an SN ratio by combining addition reading and thin-out reading by signal processing similar to signal processing using thin-out reading. First, as illustrated in the left side of the drawing, G pixel and B pixel, which are sub-colors, of the top row of regions Z1, Z2 are subjected to thin-out reading. Next, for W pixels of the main color arranged in a checkerboard pattern in the regions Z1, Z2, two pixels tied by a straight line in the drawing are subjected to addition reading at the same tone timing. For W pixels of the main color arranged in a checkerboard pattern in regions Z3, Z4, two pixels tied by a straight line in the drawing are also subjected to addition reading at the same tone timing. R and G pixels, which are sub-colors, of the lower stage of the regions Z3, Z4 are read.

Abstract: A solid-state image pickup device includes a pixel array including pixels, each having a photoelectric conversion element and a detecting unit detecting an acquired electric signal, arranged in a matrix, a signal line provided for each column of the pixel array and connected to the detecting unit through a switching element, a selection line provided for each row of the pixel array and supplied with a selection pulse causing the switching element to conduct, a resetting unit provided in each pixel constituting the pixel array and applying a predetermined potential to the detecting unit of the pixel, and an output control unit provided in each pixel constituting the pixel array and causing the switching element of the pixel to conduct according to the selection pulse supplied to another selection line connected to another switching element of another pixel belonging to another row.

Abstract: There is provided a signal processing device including a correction processing unit that acquires a pixel signal output from a sensor on which pixels are disposed in an array in which a spatial frequency of a color pixel which is a pixel acquiring a color component is lower than a spatial frequency of luminance pixels which are pixels acquiring luminance components, and then corrects the pixel signal output from a defective pixel out of the pixels that the sensor includes. During correction of a pixel signal of the color pixel, the correction processing unit performs correction referring to pixel signals of the luminance pixels having a spatial frequency higher than the spatial frequency of the color pixel.

Abstract: A solid-state imaging device includes: a pixel array unit formed by two-dimensionally disposing a plurality of pixels each having a photoelectric conversion portion; one or more SRAMs; a memory control section controlling writing of pixel data sequentially output from the pixel array unit into the SRAM and controlling readout of the pixel data from the SRAM; a correction process section performing a process of correcting the pixel data read from the SRAM by the memory control section; a defect detecting section detecting a defective address in the SRAM; and a defect relieving section holding pixel data to be written in the defective address of the SRAM by the memory control section and outputting the pixel data held therein to the correction process section instead of the pixel data which has been written in the defective address of the SRAM.

Abstract: A solid-state imaging device includes: a pixel array section having a two-dimensional array of pixels each having a photoelectric conversion section; a memory storing pixel data output from the pixel array section; a correction section reading the pixel data from the memory, and performing a correction process on the pixel data; a control section controlling writing and reading of data into and from the memory; an external interface to output the pixel data subjected to the correction process; and a test-data output section outputting test data. The control section writes the test data in a same writing sequence as a sequence of writing the pixel data output from the pixel array section into the memory, and reads the test data in a same reading sequence as a sequence of reading the pixel data output from the pixel array section from the memory, and outputting the pixel data via the external interface.

Abstract: A solid-state imaging device includes a pixel array unit in which pixels having photoelectric converting elements configured to accumulate electric signals in accordance with the quantity of received light and detecting units configured to detect the electric signals accumulated using the photoelectric converting elements are arrayed in a matrix and a timing signal generator configured to generate a timing signal with which an electric signal accumulation time period of each of respective pixels constituting the pixel array unit is set to be a time period obtained by adding a time period calculated on the basis of a position where each of the respective pixels constituting the pixel array unit is arranged to a predetermined time period.

Abstract: A solid-state imaging device includes: a pixel array unit formed by two-dimensionally disposing a plurality of pixels each having a photoelectric conversion portion; one or more SRAMs; a memory control section controlling writing of pixel data sequentially output from the pixel array unit into the SRAM and controlling readout of the pixel data from the SRAM; a correction process section performing a process of correcting the pixel data read from the SRAM by the memory control section; a defect detecting section detecting a defective address in the SRAM; and a defect relieving section holding pixel data to be written in the defective address of the SRAM by the memory control section and outputting the pixel data held therein to the correction process section instead of the pixel data which has been written in the defective address of the SRAM.

Abstract: A solid-state imaging device includes: a pixel array section having a two-dimensional array of pixels each having a photoelectric conversion section; a memory storing pixel data output from the pixel array section; a correction section reading the pixel data from the memory, and performing a correction process on the pixel data; a control section controlling writing and reading of data into and from the memory; an external interface to output the pixel data subjected to the correction process; and a test-data output section outputting test data. The control section writes the test data in a same writing sequence as a sequence of writing the pixel data output from the pixel array section into the memory, and reads the test data in a same reading sequence as a sequence of reading the pixel data output from the pixel array section from the memory, and outputting the pixel data via the external interface.

Abstract: A solid-state image pickup device includes a pixel array including pixels, each having a photoelectric conversion element and a detecting unit detecting an acquired electric signal, arranged in a matrix, a signal line provided for each column of the pixel array and connected to the detecting unit through a switching element, a selection line provided for each row of the pixel array and supplied with a selection pulse causing the switching element to conduct, a resetting unit provided in each pixel constituting the pixel array and applying a predetermined potential to the detecting unit of the pixel, and an output control unit provided in each pixel constituting the pixel array and causing the switching element of the pixel to conduct according to the selection pulse supplied to another selection line connected to another switching element of another pixel belonging to another row.

Abstract: A solid-state imaging device includes a pixel array unit in which pixels having photoelectric converting elements configured to accumulate electric signals in accordance with the quantity of received light and detecting units configured to detect the electric signals accumulated using the photoelectric converting elements are arrayed in a matrix and a timing signal generator configured to generate a timing signal with which an electric signal accumulation time period of each of respective pixels constituting the pixel array unit is set to be a time period obtained by adding a time period calculated on the basis of a position where each of the respective pixels constituting the pixel array unit is arranged to a predetermined time period.

Abstract: A method of designating an output “don't care”, includes the steps of reading (21) first data about a logic circuit in which outputs associated a plurality of inputs are described, reading (22) “don't care” indicating data which outputs a predetermined logic value in response only to a specific input among the plurality of inputs, converting (23) the first data into second data having a form conforming to an application, converting (24) the “don't care” indicating data into third data having the form, coupling (25) the plurality of inputs in the second data to associated inputs in the third data, and detecting (26) an output in the second data which output is associated with an input in response to which the predetermined logic value is output from the “don't care” indicating data.

Abstract: A logic synthesis constraint generating method for generating a delay constraint for a logical circuit having a hierarchical structure of blocks, comprises a step of receiving information of a logical circuit including the hierarchical structure divided by the block, an internal delay of each block, and a delay between the blocks, a delay distributing constraint of the logical circuit, and the target library information of the logical circuit; a step of storing the received information of the logical circuit, delay distributing constraint of the logical circuit, and target library information of the logical circuit; a step of performing a timing analysis on the information of the logical circuit and the delay distributing constraint of the logical circuit stored in the circuit database process; and a step of, when distributing the delay distributing constraint of the logical circuit as a logic synthesis delay constraint, receiving the ratio of each delay at a lower hierarchy excepting the delay of a circuit t

Abstract: A method of designating an output “don't care”, includes the steps of reading (21) first data about a logic circuit in which outputs associated a plurality of inputs are described, reading (22) “don't care” indicating data which outputs a predetermined logic value in response only to a specific input among the plurality of inputs, converting (23) the first data into second data having a form conforming to an application, converting (24) the “don't care” indicating data into third data having the form, coupling (25) the plurality of inputs in the second data to associated inputs in the third data, and detecting (26) an output in the second data which output is associated with an input in response to which the predetermined logic value is output from the “don't care” indicating data.