Abstract: An electric current measurement method is provided with: a first controlling process of sweeping a sensing current in a negative magnetization direction in a condition that a core is saturated magnetically in a positive magnetization direction; a second controlling process of sweeping the sensing current in the positive magnetization direction in a condition that the core is saturated magnetically in the negative magnetization direction; a first specifying process of specifying a value of the sensing current if the core is demagnetized in the first controlling process; a second specifying process of specifying a value of the sensing current if the core is demagnetized in the second controlling process; and a calculating process of calculating a value of a target electric current on the basis of the specified current values, the first and second controlling processes being performed repeatedly.

Abstract: A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction.

Abstract: An electric current measurement method is provided with: a first controlling process of sweeping a sensing current in a negative magnetization direction in a condition that a core is saturated magnetically in a positive magnetization direction; a second controlling process of sweeping the sensing current in the positive magnetization direction in a condition that the core is saturated magnetically in the negative magnetization direction; a first specifying process of specifying a value of the sensing current if the core is demagnetized in the first controlling process; a second specifying process of specifying a value of the sensing current if the core is demagnetized in the second controlling process; and a calculating process of calculating a value of a target electric current on the basis of the specified current values, the first and second controlling processes being performed repeatedly.

Abstract: A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction.

Abstract: The present invention presents a stencil mask in which various surface patterns can be formed, and in which deformation is suppressed when charged particles are introduced. A stencil mask of the present invention is provided with a semiconductor stack. A first penetrating hole corresponding to an ion introducing area is formed in a first semiconductor layer of the semiconductor stack, and second penetrating holes are formed in a second semiconductor layer, these second penetrating holes having a width greater than the width of the first penetrating hole. The first penetrating hole and the second penetrating holes communicate and pass through the semiconductor stack. Beam members extending between adjacent second penetrating holes connect portions of the first semiconductor layer separated by the first penetrating hole.

Abstract: A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.

Abstract: [Problem to be Solved] An object is to provide an art for preventing an element formative layer (active layer) from peeling off from a buried insulating film (intermediate insulating layer) with regard to production method of a semiconductor substrate having trench construction.

Abstract: A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.

Abstract: The present invention presents a stencil mask in which various surface patterns can be formed, and in which deformation is suppressed when charged particles are introduced. A stencil mask of the present invention is provided with a semiconductor stack. A first penetrating hole corresponding to an ion introducing area is formed in a first semiconductor layer of the semiconductor stack, and second penetrating holes are formed in a second semiconductor layer, these second penetrating holes having a width greater than the width of the first penetrating hole. The first penetrating hole and the second penetrating holes communicate and pass through the semiconductor stack. Beam members extending between adjacent second penetrating holes connect portions of the first semiconductor layer separated by the first penetrating hole.