Patents by Inventor Hideki Tsunoda

Hideki Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150119
    Abstract: A lifting device 8 with excellent transportability is provided. The lifting device 8 includes a first lifting unit 6 and a second lifting unit 7 disposed above the first lifting unit 6. The first lifting unit 6 includes a base 61, a first lifting platform 62 disposed above the base 61, and a first lifting system 63 which is provided between the base 61 and the first lifting platform 62 and which raises and lowers the first lifting platform 62. The second lifting unit 7 includes a second lifting platform 72 disposed above the first lifting platform 62, and a second lifting system 73 which raises and lowers the second lifting platform 72.
    Type: Application
    Filed: March 4, 2022
    Publication date: May 9, 2024
    Inventors: Masaru Tsunoda, Mototaka TAJIKA, Hideki KIMURA
  • Publication number: 20240150157
    Abstract: The drive device of the lifting apparatus includes an electric actuator 91, a movable part 93 that is driven and moved by an electric actuator 91, a first link member 951L (951R), a second link member 953L (953R) rotatably coupled to the first link member 951L (951R) via a shaft member 952L (952R), and a guide member 97L (97R) having a guide hole 971L (971R) for guiding the shaft member 952L (952R) that moves with the movement of the movable part 93. The lifting platform 50 is raised and lowered by vertically extending and retracting a pair of lower right and left X-shaped arms 71L (71R) and a pair of upper right and left X-shaped arms 75L (75R) via the first link member 951L and second link member 953L along with movement of the movable part 93.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 9, 2024
    Inventors: Chi ZHU, Peirng LI, Hideki KIMURA, Mototaka TAJIKA, Masaru TSUNODA
  • Publication number: 20070164809
    Abstract: A constant current is formed by supplying voltage differences between bases and emitters of a first transistor which allows a first current to flow in the emitter thereof and a second transistor which allows a second current having a current density larger than a current density of the first transistor to flow in an emitter thereof to a first resistance. A second resistance is provided on a ground potential side of a circuit in series with the first resistance. A third and a fourth resistances are provided between collectors and the power supply voltages of the first transistor and the second transistor. Both collector voltages of the first and second transistors are supplied to a differential amplifier circuit having the CMOS constitution thus forming an output voltage and, at the same time, the output voltage is supplied to bases of the first transistor and the second transistor in common.
    Type: Application
    Filed: December 2, 2004
    Publication date: July 19, 2007
    Inventors: Keiko Fukuda, Mitsuru Hiraki, Masashi Horiguchi, Takesada Akiba, Shuzo Ichiki, Hideki Tsunoda, Akihiro Kitagawa
  • Patent number: 5642252
    Abstract: An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved.The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: June 24, 1997
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Kozo Sakamoto, Isao Yoshida, Shigeo Otaka, Tetsuo Iijima, Harutora Shono, Ken Uchid, Masayoshi Kobayashi, Hideki Tsunoda
  • Patent number: 5638246
    Abstract: In a semiconductor device including a power MOSFET (M.sub.0) for the output stage, a temperature detection circuit produces an output signal upon detecting an abnormal rise in the chip temperature, the signal turns on a set input element (M.sub.1) in a latch circuit so that the latch circuit becomes a set state, the set output of the latch circuit turns on a control element (M.sub.5), causing the power MOSFET to become non-conductive so that it is protected from destruction. The latch circuit is not brought to a reset state even if the external gate terminal of the device is brought to zero volt. With a voltage outside the range of the normal input signal, e.g., a large negative voltage, being applied to the external gate terminal, the gate capacitance of the control element (M.sub.5) discharges, and consequently the latch circuit is brought to the reset state and the protective operation is cancelled.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: June 10, 1997
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Kozo Sakamoto, Isao Yoshida, Masatoshi Morikawa, Shigeo Ohtaka, Hideki Tsunoda