Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: The semiconductor integrated circuit includes a first transistor which flows a current from a high voltage source to a first node, a second transistor which flows a current from the first node to a low voltage source. Furthermore, a first inverter receives an input signal and drives the first node based on this input signal, and a second inverter drives a second node based on a voltage of the first node.

Abstract: A driver circuit generates two control signals that change from low to high as an input signal changes from high to low, and change from high to low as the input signal changes from low to high. The driver circuit also generates another two control signals that change from high to low as the input signal changes from high to low, and change from low to high as the input signal changes from low to high. The driver circuit applies these four control signals to gate terminals of four MOS transistors. Timings of logical level changes of these four control signals are controlled so as to generate a period in which the four MOS transistors are simultaneously turned on or off.

Abstract: A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.

Abstract: A driver circuit generates two control signals that change from low to high as an input signal changes from high to low, and change from high to low as the input signal changes from low to high. The driver circuit also generates another two control signals that change from high to low as the input signal changes from high to low, and change from low to high as the input signal changes from low to high. The driver circuit applies these four control signals to gate terminals of four MOS transistors. Timings of logical level changes of these four control signals are controlled so as to generate a period in which the four MOS transistors are simultaneously turned on or off.

Abstract: A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.

Abstract: The semiconductor integrated circuit includes a first transistor which flows a current from a high voltage source to a first node, a second transistor which flows a current from the first node to a low voltage source. Furthermore, a first inverter receives an input signal and drives the first node based on this input signal, and a second inverter drives a second node based on a voltage of the first node.