Patents by Inventor Hideki Yagita
Hideki Yagita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6344826Abstract: When the antenna is extended, the length of the ½&lgr; whip antenna 102 operates as an antenna thus causing only a negligible quantity of high-frequency currents to flow into the ground for the circuit board 108. When the antenna is housed, the entire length of a ¼&lgr; helical antenna 101 and a ¼&lgr; radial 109 operates as an antenna thus causing only a negligible quantity of high-frequency currents to flow into the ground for the circuit board 108. When the antenna is extended, the second contact 104 makes adjustments so that high-frequency electric signals from the ½&lgr; whip antenna 102 may be transmitted to the circuit board 108 and matching may be provided at the second matching section 106 when the antenna is extended.Type: GrantFiled: September 27, 2000Date of Patent: February 5, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Iwao Matsuura, Hideki Yagita, Hideo Nagata
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Patent number: 6292148Abstract: When the antenna is extended, the length of the ½&lgr; whip antenna 102 operates as an antenna thus causing only a negligible quantity of high-frequency currents to flow into the ground for the first circuit board 106. When the antenna is housed, the entire length of a ¼&lgr; helical antenna 101 and a metalized ¼&lgr; radial of the first enclosure 103 operates as an antenna thus causing only a negligible quantity of high-frequency currents to flow into the ground for the first circuit board 106. Because the length of the antenna is ½&lgr; both when the antenna is extended and housed, only a negligible quantity of high-frequency currents to flow into the high-frequency circuit via the ground for the first circuit board 106.Type: GrantFiled: September 27, 2000Date of Patent: September 18, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Iwao Matsuura, Hideki Yagita, Tadahisa Kamiya
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Patent number: 5901345Abstract: The output of a digital modulator is put into a power amplifying device, is distributed into n pieces in an n-power divider in the power amplifier, passes through n input phase shifters differing individually in the phase change amount, is amplified by n power amplifiers, passes through n output phase shifters to match the phase of n signals, is combined in an n-power combiner, and is issued from an output terminal to a phase shifter, and the output of the phase shifter is issued to a transmission antenna.Type: GrantFiled: April 6, 1998Date of Patent: May 4, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hikaru Ikeda, Hiroaki Kosugi, Kaoru Ishida, Nobuo Fuse, Hideki Yagita, Hiroshi Haruki
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Patent number: 5770970Abstract: The output of a digital modulator is put into a power amplifying device, is distributed into n pieces in an n-power divider in the power amplifier, passes through n input phase shifters differing individually in the phase change amount, is amplified by n power amplifiers, passes through n output phase shifters to match the phase of n signals, is combined in an n-power combiner, and is issued from an output terminal to a phase shifter, and the output of the phase shifter is issued to a transmission antenna.Type: GrantFiled: August 30, 1996Date of Patent: June 23, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hikaru Ikeda, Hiroaki Kosugi, Kaoru Ishida, Nobuo Fuse, Hideki Yagita, Hiroshi Haruki
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Patent number: 5514883Abstract: A field effect transistor is disclosed. The field effect transistor includes: a semiconductor substrate having at least an upper face; a semiconductor layered structure, formed on the upper face of the semiconductor substrate, the semiconductor layered structure including a channel layer; a source electric formed on the semiconductor layered structure; a drain electrode formed on the semiconductor layered structure at a position apart from the source electrode in a first direction by a prescribed distance; and a gate electrode, formed on the semiconductor layered structure between the source electrode and the drain electrode.Type: GrantFiled: January 6, 1995Date of Patent: May 7, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadayoshi Nakatsuka, Kaoru Inoue, Hiromasa Fujimoto, Hideki Yagita
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Patent number: 5339458Abstract: In order to provide a high-gain low-distortion low-consumption-current frequency converter circuit employing an FET and an integrated solid-state unit thereof, an FET type having a large K value and a high gain is used in an oscillator section 180 while another FET type having a small K value and a low distortion is used in an amplifier section 182. The K value of the FET is a parameter measured in microamperes per square volt, expressed in the equationIds=K(Vgs-Vth).sup.2where Ids represents the drain current of the FET, Vgs represents the voltage across the gate and the source, and Vth represents the threshold level of the FET. The above construction enables forming a high-gain LO section and a low-distortion RF section at the same time thereby to enable integrating a frequency converter circuit having a high gain, a low distortion, and a low consumption current on a semiconductor board.Type: GrantFiled: June 12, 1992Date of Patent: August 16, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadayoshi Nakatsuka, Hideki Yagita
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Patent number: 5319318Abstract: A gain control circuit includes a first FET for serving as an active load, a second FET serving as an amplifier, and a third FET for serving as a current source. The first, second, and third FETs have substantially the same characteristics and are mutually connected in a series. The gain control circuit further includes a fourth FET for serving as a variable active load connected in parallel with the third FET and a capacitor connected between the third and fourth FETs. The fourth FET is also connected to a gain control terminal. The gain of the second FET is controlled by the voltage applied to the gate of the fourth FET through said gain control line.Type: GrantFiled: August 18, 1992Date of Patent: June 7, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Taketo Kunihisa, Yukio Sakai, Kazuhiro Yahata, Tadayoshi Nakatsuka, Hideki Yagita
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Patent number: 5210504Abstract: A semiconductor device for a tuner capable of simultaneously satisfying a low noise factor, low third order distortion characteristics and low power consumption, and a tuner using this semiconductor device for a tuner and capable of reducing the size and eliminating labor during assembly. The semiconductor device is a variable gain amplification circuit comprising a gate grounded circuit using a transistor, and a differential amplification circuit including transistors and constant current sources. Transistors are used as variable resistance devices, and the gain of the gate grounded circuit can be varied by changing the gate voltage of a transistor. The gain of the differential amplification circuit can be varied by changing the gate voltage of another transistor. The overall gain of the circuit can be varied within a necessary range by simultaneously operating these gain controls, and the third order distortion can be improved monotonously with the decrease of the gain.Type: GrantFiled: March 16, 1992Date of Patent: May 11, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Yagita, Tadayoshi Nakatsuka, Taketo Kunihisa, Michiaki Tsuneoka, Yukio Sakai, Kazuhiro Yahata