Patents by Inventor Hideki Yoneda

Hideki Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for trading a manufacturing capacity and manufacturing capacity trading system
    Publication number: 20010037282
    Abstract: The invention provides means to enable stable operation rates of the industries which needs huge facilities.
    Type: Application
    Filed: March 19, 2001
    Publication date: November 1, 2001
    Inventor: Hideki Yoneda
  • Neural network processor including systolic array of two-dimensional layers
    Patent number: 5627943
    Abstract: The invention provides a pattern recognition processing apparatus and a technique for realizing a neural network of a complex structure within the processing apparatus. The apparatus includes a neural network having two-dimensional layers connected to form a feed-forward systolic array. Each two dimensional layer includes a feature extraction layer connected with a positional error absorbing layer. A host system provides inputs to the network. Each layer within the network includes processing elements such as a MOS analog circuit that receives input voltage signals and provides output voltage signals.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: May 6, 1997
    Assignees: Kawasaki Steel Corporation, The Texas A&M University System
    Inventors: Hideki Yoneda, Edgar Sanchez-Sinencio
  • Neural network, processor, and pattern recognition apparatus
    Patent number: 5519811
    Abstract: Apparatus for realizing a neural network of a complex structure, such as the Neocognitron, in a neural network processor comprises processing elements corresponding to the neurons of a multilayer feed-forward neural network. Each of the processing elements comprises an MOS analog circuit that receives input voltage signals and provides output voltage signals. The MOS analog circuits are arranged in a systolic array.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: May 21, 1996
    Assignee: Kawasaki Steel Corporation
    Inventors: Hideki Yoneda, Edgar Sanchez-Sinencio
  • Memory module, method for control thereof and method for setting fault bit table for use therewith
    Patent number: 5315552
    Abstract: A memory module implementing a desired memory capacity by use of a plurality of memory chips. The memory module has a fault bit substituting device that compensates for fault bits detected in any of the memory chips. This improves the yield of the memory module and lowers the production costs thereof without recourse to expensive equipment such as wafer processors.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: May 24, 1994
    Assignee: Kawasaki Steel Corporation
    Inventor: Hideki Yoneda
  • Filler for patterning of ceramics product and process for producing the same
    Patent number: 5066333
    Abstract: A filler for patterning of ceramics product, comprising a slip composed mainly of a ceramics base material having a binder and a pigment added therein formed into particulate.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: November 19, 1991
    Assignee: Toto Ltd.
    Inventors: Yutaka Tomioka, Satoru Nakanishi, Seizi Shintake, Hideki Yoneda