Abstract: Pressure measurement system has inside a main body to be mounted on an object to be measured: a sensor section; a control section processing an input from the sensor section and outputting a predetermined signal; a vacuum gauge provided with power supply circuit sections for providing the control section and the sensor section with power; and a terminal device being connectable to the control section, through a communication line, in a manner to be freely communicated with each other and being capable of supplying the power circuit section with power. The vacuum gauge is arranged to be able to judge the power supply from the terminal device to the control section. When power is supplied from the terminal device to the control section, the control section and the terminal device are connected together through the communication line so as to be freely communicated with each other.

Abstract: Pressure measurement system has inside a main body to be mounted on an object to be measured: a sensor section; a control section processing an input from the sensor section and outputting a predetermined signal; a vacuum gauge provided with power supply circuit sections for providing the control section and the sensor section with power; and a terminal device being connectable to the control section, through a communication line, in a manner to be freely communicated with each other and being capable of supplying the power circuit section with power. The vacuum gauge is arranged to be able to judge the power supply from the terminal device to the control section. When power is supplied from the terminal device to the control section, the control section and the terminal device are connected together through the communication line so as to be freely communicated with each other.

Abstract: An oxygen detection method, includes: preparing a grid, an ion collector, and a filament in which an oxide are formed on a surface of metal; controlling a filament current flowing to the filament so that an emission current becomes constant; discharging thermionic electrons which are caused by heat generation by applying the filament current, and generating ions by ionizing a gas; capturing the ions with the ion collector; and detecting oxygen being present in a vacuum processing chamber by measuring a filament current value.

Abstract: An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

Abstract: An oxygen detection method, includes: preparing a grid, an ion collector, and a filament in which an oxide are formed on a surface of metal; controlling a filament current flowing to the filament so that an emission current becomes constant; discharging thermionic electrons which are caused by heat generation by applying the filament current, and generating ions by ionizing a gas; capturing the ions with the ion collector; and detecting oxygen being present in a vacuum processing chamber by measuring a filament current value.

Abstract: A disclosed signal transmitting method includes the steps of a) categorizing plural digital signals, obtained by performing A/D conversion on plural analog signals consecutively arranged in a time direction, into plural signal groups in an order starting from lower bits of the plural digital signals, b) performing code spreading on the plural digital signals by using a different spread frequency for each signal group and using different spread codes for each bit, c) multiplexing the spread digital signals, and d) transmitting the multiplexed plural digital signals.

Abstract: A multiprocessor of a single processor, including a pipeline processing unit which successively fetches an instruction sequence to be independently processed on each of the multiprocessor with a shifted phase in one cycle.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

Abstract: A disclosed signal transmitting method includes the steps of a) categorizing plural digital signals, obtained by performing A/D conversion on plural analog signals consecutively arranged in a time direction, into plural signal groups in an order starting from lower bits of the plural digital signals, b) performing code spreading on the plural digital signals by using a different spread frequency for each signal group and using different spread codes for each bit, c) multiplexing the spread digital signals, and d) transmitting the multiplexed plural digital signals.

Abstract: A mass spectrometer is provided which is mounted on a wall portion of a chamber and analyzes a gas to be analyzed existing in the chamber. The mass spectrometer includes: a measurement unit which is inserted into the chamber at the time of mounting the mass spectrometer to the chamber and measures each partial pressure of gaseous components in the gas to be analyzed with respect to mass-to-charge ratios; a control unit which is disposed outside of the wall portion at the time of mounting the mass spectrometer on the chamber and is used to manipulate the measurement unit; and a display unit which is disposed outside of the wall portion at the time of mounting the mass spectrometer on the chamber and displays the measurement result of the measurement unit. Here, the measurement unit, the control unit, and the display unit are disposed close to each other.

Abstract: In a method of manufacturing a liquid crystal panel including a panel assembly, a nozzle mechanism is located at a vicinity of a liquid crystal filling port of the panel assembly with leaving a space between an intake of the nozzle mechanism and the liquid crystal filling port. The nozzle mechanism sucks surrounding gaseous to generate negative pressure and a continuous gaseous flow around the liquid crystal filling port. The negative pressure discharges an excess of liquid crystal filled in the panel assembly while the continuous gaseous flow blows the discharged liquid crystal. The blown liquid crystal is sucked into the intake of the panel assembly. Thus, a gap of the panel assembly is adjusted within a proper range in a short time.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: In a method of manufacturing a liquid crystal panel including a panel assembly, a nozzle mechanism is located at a vicinity of a liquid crystal filling port of the panel assembly with leaving a space between an intake of the nozzle mechanism and the liquid crystal filling port. The nozzle mechanism sucks surrounding gaseous to generate negative pressure and a continuous gaseous flow around the liquid crystal filling port. The negative pressure discharges an excess of liquid crystal filled in the panel assembly while the continuous gaseous flow blows the discharged liquid crystal. The blown liquid crystal is sucked into the intake of the panel assembly. Thus, a gap of the panel assembly is adjusted within a proper range in a short time.

Abstract: A processor architecture includes a program counter which executes M independent program streams in time division in units of one instruction, a pipeline which is shared by each of the program streams and has N pipeline stages operable at a frequency F, and a mechanism which executes only s program streams depending on a required operation performance, where M and N are integers greater than or equal to one and having no mutual dependency, s is an integer greater than or equal to zero and satisfying s≦M. An apparent number of pipeline stages viewed from each of the program streams is set to N/M so that M parallel processors having an apparent operating frequency F/M are formed.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: A processor is efficiently controlled and the electric power required to drive the processor is reduced by switching between a process of driving a plurality of arithmetic units using a series of instructions from an instruction control unit and a process of driving a plurality of arithmetic units using a plurality of series of instructions from different instruction control units according to an object to be processed. When a plurality of instruction control units 10, 11 and 12 drive a plurality of arithmetic units 13, 14 and 15, a synchronous execution process of driving the plurality of arithmetic units 13, 14 and 15 using the series of instructions from the first instruction control unit 10 is switched to/from an independent execution process of driving the arithmetic units 13, 14 and 15 using the series of instructions from the instruction control units 10, 11 and 12, respectively, according to the information contained in the series of instructions.

Abstract: An information processing apparatus includes a dedicated graphic hardware part dedicated to execution of a specific process function under a pipeline process scheme, and a microprogram execution part executing a process using a microprogram. When three-dimensional graphic information is processed, a process for determining endpoints is executed by the microprogram execution part, and an interpolation process started from an endpoint is executed by the dedicated graphic hardware part for each endpoint process. While the dedicated graphic hardware part is executing the interpolation process, the microprogram execution part is operated in parallel so as to execute the endpoint process for a next endpoint.

Abstract: A prediction block address is generated from a current block address in accordance with a rule specified by a prediction mode signal. One of two cache memory banks is allocated as a current bank and the other is allocated as a prediction bank. When the current block address is stored in the prediction bank, the allocation of the current and prediction banks is reversed. When the prediction block address is not stored in the prediction bank, a data block specified by the prediction block address is block-read into the prediction bank.