Abstract: A semiconductor integrated circuit apparatus includes a main clock generation circuit that generates a main clock signal, a plurality of function blocks, a clock generation circuit in the plurality of function blocks, and a phase locked loop circuit in the clock generation circuit. The phase locked loop circuit generates a clock signal in the plurality of function blocks, using the main clock signal from the main clock generation circuit.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: A semiconductor integrated circuit apparatus includes a main clock generation circuit that generates a main clock signal, a plurality of function blocks, a clock generation circuit in the plurality of function blocks, and a phase locked loop circuit in the clock generation circuit. The phase locked loop circuit generates a clock signal in the plurality of function blocks, using the main clock signal from the main clock generation circuit.

Abstract: A semiconductor integrated circuit apparatus that enables function blocks in a semiconductor integrated circuit freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves. In a semiconductor integrated circuit apparatus 100, a first function block 110 has a first clock generation circuit 111 that generates a first system clock supplied to circuitry in a function block, first internal memory 112 in which data is read/written by means of the first system clock, and a selector 113 that selects the first system clock or a second system clock and supplies the selected clock to first internal memory 112. A clock selected by selector 113 from the first system clock or the second system clock is supplied as the clock supplied to first internal memory 112.

Abstract: A semiconductor integrated circuit apparatus includes a first circuit block including a critical path and second and third circuit blocks not including the critical path. A threshold voltage of a semiconductor element of a circuit in the first circuit block is equal to or lower than a threshold voltage of a semiconductor element of a circuit in the second circuit block and a supply voltage supplied to the first circuit block is equal to or higher than a supply voltage supplied to the second circuit block, wherein the critical path in the first circuit block is eliminated. A threshold voltage of a semiconductor element of a circuit in the third circuit block is equal to or lower than the threshold voltage of the semiconductor element of the circuit in the second circuit block, and a supply voltage supplied to the third circuit block is equal to or lower than the supply voltage supplied to the second circuit block, wherein power consumption of the third circuit block is reduced.

Abstract: A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks are composed of MIS transistors fabricated on an SOI structure silicon substrate and have at least one potential set including a high-potential side potential, a low-potential side potential, a substrate potential of a P-channel MIS transistor, and a substrate potential of an N-channel MIS transistor.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks (400a to 400n) are composed of MIS transistors fabricated on an SOI structure silicon substrate and have at least one potential set including a high-potential side potential, a low-potential side potential, a substrate potential of a P-channel MIS transistor, and a substrate potential of an N-channel MIS transistor.

Abstract: A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit blocks 41 through 48 that do not include a critical path, second circuit blocks 51 through 54 that include a critical path, first power supply wiring 25 that supplies a first power supply to first circuit blocks 41 through 48, and second power supply wiring 26 that supplies a second power supply of higher voltage than the first power supply to second circuit blocks 51 through 54, with second circuit blocks 51 through 54 being connected to second power supply wiring 26 by means of wiring areas 61 through 64 respectively, and being supplied with the second power supply.

Abstract: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block 61 does include a critical path. First power supply wiring 28 supplies a first power supply and second power supply wiring 29 supplies a second power supply of a high-voltage compared to the first power supply. A wiring section 71 (P-channel first substrate power supply wiring and P-channel first power supply wiring) supplies the first power supply as a substrate power supply for P-channel elements of the first circuit block 51 and a source power supply.

Abstract: A semiconductor integrated circuit apparatus that enables function blocks in a semiconductor integrated circuit freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves. In a semiconductor integrated circuit apparatus 100, a first function block 110 has a first clock generation circuit 111 that generates a first system clock supplied to circuitry in a function block, first internal memory 112 in which data is read/written by means of the first system clock, and a selector 113 that selects the first system clock or a second system clock and supplies the selected clock to first internal memory 112. A clock selected by selector 113 from the first system clock or the second system clock is supplied as the clock supplied to first internal memory 112.

Abstract: A semiconductor integrated circuit apparatus, electronic apparatus and method of manufacturing the semiconductor integrated circuit apparatus capable of achieving low power consumption without forming a critical path.

Abstract: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block 61 does include a critical path. First power supply wiring 28 supplies a first power supply and second power supply wiring 29 supplies a second power supply of a high-voltage compared to the first power supply. A wiring section 71 (P-channel first substrate power supply wiring and P-channel first power supply wiring) supplies the first power supply as a substrate power supply for P-channel elements of the first circuit block 51 and a source power supply.

Abstract: A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit blocks 41 through 48 that do not include a critical path, second circuit blocks 51 through 54 that include a critical path, first power supply wiring 25 that supplies a first power supply to first circuit blocks 41 through 48, and second power supply wiring 26 that supplies a second power supply of higher voltage than the first power supply to second circuit blocks 51 through 54, with second circuit blocks 51 through 54 being connected to second power supply wiring 26 by means of wiring areas 61 through 64 respectively, and being supplied with the second power supply.