Patents by Inventor Hideko Ando
Hideko Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8076771Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.Type: GrantFiled: June 26, 2008Date of Patent: December 13, 2011Assignee: Renesas Electronics CorporationInventor: Hideko Ando
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Publication number: 20090001555Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.Type: ApplicationFiled: June 26, 2008Publication date: January 1, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Hideko ANDO
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Patent number: 7035081Abstract: The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise.Type: GrantFiled: May 28, 2002Date of Patent: April 25, 2006Assignee: Hitachi, Ltd.Inventors: Tatsuya Nagata, Seiji Miyamoto, Hideko Ando
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Patent number: 6911734Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: GrantFiled: March 20, 2003Date of Patent: June 28, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Patent number: 6911733Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: GrantFiled: February 26, 2003Date of Patent: June 28, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Publication number: 20040169198Abstract: The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise.Type: ApplicationFiled: November 25, 2003Publication date: September 2, 2004Inventors: Tatsuya Nagata, Seiji Miyamoto, Hideko Ando
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Patent number: 6747356Abstract: Control of the characteristic impedance of wirings is performed with high accuracy.Type: GrantFiled: March 13, 2003Date of Patent: June 8, 2004Assignee: Hitachi, Ltd.Inventors: Hideko Ando, Seiji Miyamoto
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Publication number: 20030231088Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: ApplicationFiled: February 26, 2003Publication date: December 18, 2003Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Publication number: 20030218238Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: ApplicationFiled: March 20, 2003Publication date: November 27, 2003Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Publication number: 20030173640Abstract: Control of the characteristic impedance of wirings is performed with high accuracy.Type: ApplicationFiled: March 13, 2003Publication date: September 18, 2003Applicant: Hitachi, Ltd.Inventors: Hideko Ando, Seiji Miyamoto
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Patent number: 6433412Abstract: A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.Type: GrantFiled: March 8, 2001Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Hideko Ando, Hiroshi Kikuchi, Ikuo Yoshida, Toshihiko Sato, Tomo Shimizu
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Patent number: 6380621Abstract: An electrically reliable heat radiating package provided with ball grid array (BGA) structure and a method of manufacturing the package are disclosed. In the concrete, a semiconductor chip is mounted on one surface of a ceramic wiring board via a first soldered bump electrode and resin is filled in a gap area between the one surface of the wiring board and the principal surface of the semiconductor chip. A heat diffusing plate formed in larger plane size than that of the semiconductor chip by aluminum nitride is arranged on the rear surface opposite to the principal surface of the semiconductor chip and soldered. Further, a radiating fin made of aluminum is provided on the heat diffusing plate and stuck via silicone rubber in which thermally conductive filler is included.Type: GrantFiled: April 5, 2000Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Hideko Ando, Hiroshi Kikuchi, Toshihiko Sato, Tetsuya Hayashida
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Publication number: 20010050428Abstract: A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 in face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions for connecting both and relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.Type: ApplicationFiled: March 8, 2001Publication date: December 13, 2001Inventors: Hideko Ando, Hiroshi Kikuchi, Ikuo Yoshida, Toshihiko Sato, Tomo Shimizu
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Patent number: 6111322Abstract: An electrically reliable heat radiating package provided with a ball grid array (BGA) structure and a method of manufacturing the package are disclosed.A semiconductor chip is mounted on one surface of a ceramic wiring board via first solder bump electrodes and resin is filled in a gap area between the one surface of the wiring board and the principal surface of the semiconductor chip. A heat diffusing plate formed in a larger plane size than that of the semiconductor chip by aluminum nitride is arranged on the rear surface opposite to the principal surface of the semiconductor chip and soldered.Further, a radiating fin made of aluminum is provided on the heat diffusing plate and struck via silicone rubber in which a thermally conductive filler is includes.Type: GrantFiled: May 19, 1997Date of Patent: August 29, 2000Assignee: Hitachi, Ltd.Inventors: Hideko Ando, Hiroshi Kikuchi, Toshihiko Sato, Tetsuya Hayashida