Patents by Inventor Hideko Andou

Hideko Andou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9355941
    Abstract: A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 31, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Hideko Andou
  • Publication number: 20150325502
    Abstract: A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 12, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideko ANDOU
  • Patent number: 9111922
    Abstract: A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: August 18, 2015
    Assignee: REnesas Electronics Corporation
    Inventor: Hideko Andou
  • Publication number: 20140103510
    Abstract: A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 17, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideko ANDOU
  • Patent number: 8310049
    Abstract: A semiconductor device includes a semiconductor chip having a current path between a first principal surface and a second principal surface opposite from the first principal surface, a first conductive frame having an opposite region to the first principal surface, and a second conductive frame electrically connected via electrical connection member to a pad formed on the second principal surface. In a gap between the first principal surface and the first conductive frame, there are arranged multiple column-shaped lead-free solders which are arranged within a circle drawn around a center of the opposite region and having a diameter corresponding to a narrow side of the opposite region, and which electrically connects the first conductive frame with the semiconductor chip, and a filler which is filled between the multiple column-shaped lead-free solders.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hideko Andou
  • Publication number: 20100181666
    Abstract: A semiconductor device includes a semiconductor chip having a current path between a first principal surface and a second principal surface opposite from the first principal surface, a first conductive frame having an opposite region to the first principal surface, and a second conductive frame electrically connected via electrical connection member to a pad formed on the second principal surface. In a gap between the first principal surface and the first conductive frame, there are arranged multiple column-shaped lead-free solders which are arranged within a circle drawn around a center of the opposite region and having a diameter corresponding to a narrow side of the opposite region, and which electrically connects the first conductive frame with the semiconductor chip, and a filler which is filled between the multiple column-shaped lead-free solders.
    Type: Application
    Filed: December 15, 2009
    Publication date: July 22, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hideko Andou
  • Publication number: 20100078803
    Abstract: A semiconductor flat package device capable of attaining a favorable operation and ensuring a sufficient spreading quality of solder for the lead top end is provided. A semiconductor chip 1 is encapsulated by an encapsulation resin. At first, a lead is half-blanked on the side of the top end of the lead protruding from the encapsulation region in the direction from the soldering surface to the printed circuit board, thereby forming a half-blanked region. Then, a plating layer is formed to the half-blanked region of the lead. Then, the lead is cut from the upper end of the half-blanked region formed with the plating layer in the direction from the soldering surface. The half-blanked region and the lead cut region form the top end face of the lead which forms a pseudo-planar face. Thus, a plating layer of a sufficient area is formed stably to the top end face of the lead. As a result, a solder fillet of a sufficient height is formed stably at the top end face of the lead.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: HIDEKO ANDOU, TOSHINORI KIYOHARA