Patents by Inventor Hideko Mukaida

Hideko Mukaida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224236
    Abstract: A semiconductor device according to an embodiment includes a substrate and a semiconductor chip. The semiconductor chip is provided over the substrate. The substrate includes a wire layer and an insulating layer. The wire layer includes a wire electrically connected to the semiconductor chip. The insulating layer is provided in contact with the wire layer and includes a glass woven fabric containing a resin. The glass woven fabric includes a plurality of glass fibers that are provided along two or more directions parallel with the glass woven fabric and are woven. The glass fibers differ in at least one of the material, number, and thickness depending on the directions parallel with the glass woven fabric.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 11, 2025
    Assignee: Kioxia Corporation
    Inventors: Hideo Aoki, Hideko Mukaida, Satoshi Tsukiyama
  • Publication number: 20240421121
    Abstract: A semiconductor device according to an embodiment includes a substrate, a first stack, a second stack, a first bonding layer, a second bonding layer, a first wire, and a second wire. The first stack has a plurality of first semiconductor chips. The second stack has a plurality of second semiconductor chips. The first bonding layer is provided at a lower part of each of the plurality of first semiconductor chips. The second bonding layer is provided at a lower part of each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chips and the second semiconductor chips to one another. The second wire electrically connects the substrate and the second semiconductor chips. The first bonding layer provided at the lower part of the first semiconductor chip in a lowest stage has a thickness different from the thickness of the other first bonding layers.
    Type: Application
    Filed: June 5, 2024
    Publication date: December 19, 2024
    Applicant: Kioxia Corporation
    Inventors: Masayuki MIURA, Kazuma HASEGAWA, Hideko MUKAIDA, Kana KUDO
  • Publication number: 20240186296
    Abstract: A semiconductor device according to the present embodiment includes a substrate having a first surface, a first spacer and a second spacer, a first semiconductor chip, and a stacked body. The first semiconductor chip is provided on the first surface so as to be disposed between the first spacer and the second spacer. The stacked body is a stacked body that is provided above the first spacer, the second spacer, and the first semiconductor chip and in which a plurality of second semiconductor chips are stacked in a first direction. One of the second semiconductor chips, which is provided on the lowermost second semiconductor chip, is stacked with an offset relative to the lowermost second semiconductor chip in a second direction. A central position of the first semiconductor chip is separated from a central position of the lowermost second semiconductor chip in the second direction.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 6, 2024
    Applicant: Kioxia Corporation
    Inventors: Akio WATANABE, Yusuke AKADA, Hideko MUKAIDA
  • Publication number: 20240188253
    Abstract: A semiconductor device according to an embodiment includes: a chamber including an internal structure capable of holding a pressure in the chamber lower than atmospheric pressure; one or a plurality of cooling member provided inside of the internal structure of the chamber, the cooling member holding and cooling a semiconductor device; and a heat transfer part exchanging heat with a refrigerator cooling the cooling member.
    Type: Application
    Filed: September 6, 2023
    Publication date: June 6, 2024
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Yasuhito YOSHIMIZU, Yusuke HIGASHI, Hideko MUKAIDA
  • Patent number: 11942176
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Xu Li, Masayuki Miura, Takayuki Miyazaki, Toshio Fujisawa, Hiroto Nakai, Hideko Mukaida, Mie Matsuo
  • Patent number: 11568901
    Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Kazushige Kawasaki, Masayuki Miura, Hideko Mukaida
  • Publication number: 20220301599
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Application
    Filed: September 15, 2021
    Publication date: September 22, 2022
    Inventors: Tomoya SANUKI, Xu LI, Masayuki MIURA, Takayuki MIYAZAKI, Toshio FUJISAWA, Hiroto NAKAI, Hideko MUKAIDA, Mie MATSUO
  • Publication number: 20220293138
    Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 15, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazushige KAWASAKI, Masayuki MIURA, Hideko MUKAIDA
  • Publication number: 20220246516
    Abstract: A semiconductor device according to an embodiment includes a substrate and a semiconductor chip. The semiconductor chip is provided over the substrate. The substrate includes a wire layer and an insulating layer. The wire layer includes a wire electrically connected to the semiconductor chip. The insulating layer is provided in contact with the wire layer and includes a glass woven fabric containing a resin. The glass woven fabric includes a plurality of glass fibers that are provided along two or more directions parallel with the glass woven fabric and are woven. The glass fibers differ in at least one of the material, number, and thickness depending on the directions parallel with the glass woven fabric.
    Type: Application
    Filed: August 30, 2021
    Publication date: August 4, 2022
    Applicant: Kioxia Corporation
    Inventors: Hideo AOKI, Hideko MUKAIDA, Satoshi TSUKIYAMA
  • Publication number: 20190067177
    Abstract: A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the package substrate. A metal bump is provided on the second surface. A package substrate is a multilayer substrate that includes first to fourth wiring layers and first to third resin layers. CTE1<CTE2<CTE3<CTE4 is satisfied where coefficients of thermal expansion of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are CTE1 to CTE4, respectively. EM1>EM3>EM2>EM4 is satisfied where elastic moduli of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are EM1 to EM4, respectively.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akira TANIMOTO, Hideko MUKAIDA, Naoko NUMATA, Kenji MIYAWAKI
  • Patent number: 10217701
    Abstract: A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the package substrate. A metal bump is provided on the second surface. A package substrate is a multilayer substrate that includes first to fourth wiring layers and first to third resin layers. CTE1<CTE2<CTE3<CTE4 is satisfied where coefficients of thermal expansion of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are CTE1 to CTE4, respectively. EM1>EM3>EM2>EM4 is satisfied where elastic moduli of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are EM1 to EM4, respectively.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akira Tanimoto, Hideko Mukaida, Naoko Numata, Kenji Miyawaki
  • Patent number: 10096574
    Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Tsukiyama, Hideko Mukaida, Yoichiro Kurita
  • Patent number: 9972600
    Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: May 15, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Tsukiyama, Hideko Mukaida, Yoichiro Kurita
  • Patent number: 9887328
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tomizawa, Akihiro Kojima, Miyoko Shimada, Yosuke Akimoto, Hideko Mukaida, Mitsuyoshi Endo, Hideto Furuyama, Yoshiaki Sugizaki, Kazuo Fujimura, Shinya Ito, Shinji Nunotani
  • Publication number: 20160365336
    Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Satoshi TSUKIYAMA, Hideko MUKAIDA, Yoichiro KURITA
  • Publication number: 20160079184
    Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventors: Satoshi TSUKIYAMA, Hideko MUKAIDA, Yoichiro KURITA
  • Patent number: 9153746
    Abstract: According to an embodiment, a semiconductor light emitting device includes a semiconductor layer having a light emitting layer. The device also includes a p-side electrode provided on a first region including the light emitting layer; an n-side electrode provided on a second region layer not including the light emitting layer; and a first insulating film having a first opening communicating with the p-side electrode and a second opening communicating with the n-side electrode. A p-side interconnection is provided on the first insulating film and electrically connected to the p-side electrode through the first opening. An n-side interconnection is provided on the first insulating film and electrically connected to the n-side electrode through the second opening. The p-side interconnection has a plurality of protrusive parts protruding toward the n-side interconnection, and the n-side interconnection has a plurality of portions extending between the protrusive parts of the p-side interconnection.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yosuke Akimoto, Hideyuki Tomizawa, Hideko Mukaida, Miyoko Shimada, Yoshiaki Sugizaki, Hideto Furuyama
  • Publication number: 20150069437
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.
    Type: Application
    Filed: July 10, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki TOMIZAWA, Akihiro KOJIMA, Miyoko SHIMADA, Yosuke AKIMOTO, Hideko MUKAIDA, Mitsuyoshi ENDO, Hideto FURUYAMA, Yoshiaki SUGIZAKI, Kazuo FUJIMURA, Shinya ITO, Shinji NUNOTANI
  • Publication number: 20150069634
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: March 2, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukifumi OYAMA, Hideko MUKAIDA, Masatoshi FUKUDA, Satoshi TSUKIYAMA, Shinya FUKAYAMA
  • Patent number: 8633602
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.8a4 a1: a logarithm of the modulus of elasticity [MPa] of the adhesive layer a2: the sink amount [mm] of the adhesive layer a3: the thickness [mm] of the protective film a4: a logarithm of the modulus of elasticity [MPa] of the protective film.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Suzuya, Atsushi Yoshimura, Hideko Mukaida