Patents by Inventor Hideko Oodaira
Hideko Oodaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8665661Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 8350309Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: December 2, 2011Date of Patent: January 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20120314497Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 20, 2012Publication date: December 13, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 8259494Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: August 12, 2010Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 8248849Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: August 12, 2010Date of Patent: August 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20120075903Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Patent number: 8084802Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: February 11, 2011Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20110134700Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: February 11, 2011Publication date: June 9, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Patent number: 7893477Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: July 27, 2007Date of Patent: February 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20100309723Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 12, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20100309722Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: August 12, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7787277Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: March 21, 2008Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7425739Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: August 5, 2005Date of Patent: September 16, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20080170424Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: March 21, 2008Publication date: July 17, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7359228Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: December 18, 2006Date of Patent: April 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Patent number: 7332762Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: December 28, 2006Date of Patent: February 19, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20080019190Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: July 27, 2007Publication date: January 24, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20070103958Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: ApplicationFiled: December 18, 2006Publication date: May 10, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome
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Publication number: 20070103983Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: December 28, 2006Publication date: May 10, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Patent number: 7151685Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.Type: GrantFiled: January 12, 2006Date of Patent: December 19, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita, Kazuhiro Shimizu, Seiichi Aritome