Patents by Inventor Hidekuni Ishida

Hidekuni Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a bipolar transistor
    Patent number: 4778772
    Abstract: A method of manufacturing a semiconductor device by forming an N type collector layer in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorous and arsenic. Arsenic or antimony or the like, which are N type impurity material of which the energy of combination with vacancies is great are diffused in the P type base layer.
    Type: Grant
    Filed: March 5, 1987
    Date of Patent: October 18, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Takahashi, Hidekuni Ishida, Toshio Yonezawa
  • NPN transistor with base double doped with arsenic and boron
    Patent number: 4667218
    Abstract: A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.
    Type: Grant
    Filed: November 19, 1980
    Date of Patent: May 19, 1987
    Assignee: Tokyo Shibaura Electric Company, Limited
    Inventors: Kouichi Takahashi, Hidekuni Ishida, Toshio Yonezawa
  • Fabrication of transistors having specifically paired dopants
    Patent number: 4263067
    Abstract: A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.
    Type: Grant
    Filed: February 21, 1980
    Date of Patent: April 21, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kouichi Takahashi, Hidekuni Ishida, Toshio Yonezawa
  • Method of reducing emitter dip in transistors utilizing specifically paired dopants
    Patent number: 4226650
    Abstract: A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.
    Type: Grant
    Filed: May 30, 1978
    Date of Patent: October 7, 1980
    Inventors: Kouichi Takahashi, Hidekuni Ishida, Toshio Yonezawa
  • Method of producing semiconductor device involving the use of silicon nitride as an oxidation mask
    Patent number: 4155802
    Abstract: A method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming an insulation film and selectively forming a second insulation film at predetermined portions by the use of a silicon nitride film as the mask.
    Type: Grant
    Filed: December 2, 1976
    Date of Patent: May 22, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Toshio Yonezawa, Hidekuni Ishida, Shunichi Hiraki, Shoichi Kitane